Arteris Releases the Latest Generation of Magillem Registers to Automate Semiconductor Hardware/Software Integration
Arteris (Nasdaq: AIP) has announced the immediate release of its next-generation Magillem Registers technology for SoC integration automation. The solution integrates Magillem 5 and Semifore CSRCompiler products into a unified platform for register management and Hardware/Software Interface automation.
Key improvements include up to 3x faster performance and 5x increased scalability compared to previous versions, supporting designs from IoT devices to complex AI SoCs. The product reduces hardware/software integration development time by 35% versus in-house solutions and features over 1,000 semantic and syntactic checks to reduce silicon failure risk.
The release expands standards support to include IEEE 1685-2022 (IP-XACT) and SystemRDL 2.0, enhancing IP reuse and third-party compatibility. The platform serves as a single source of truth for specifying, documenting, implementing, and verifying SoC address maps.
Arteris (Nasdaq: AIP) ha annunciato il rilascio immediato della sua tecnologia di Magillem Registers di nuova generazione per l'automazione dell'integrazione SoC. La soluzione integra i prodotti Magillem 5 e Semifore CSRCompiler in una piattaforma unificata per la gestione dei registri e l'automazione dell'interfaccia hardware/software.
I principali miglioramenti includono fino a 3 volte le prestazioni più veloci e 5 volte maggiore scalabilità rispetto alle versioni precedenti, supportando progetti che vanno dai dispositivi IoT ai complessi SoC AI. Il prodotto riduce il tempo di sviluppo per l'integrazione hardware/software del 35% rispetto alle soluzioni interne e presenta oltre 1.000 controlli semantici e sintattici per ridurre il rischio di guasti al silicio.
Il rilascio amplia il supporto agli standard per includere IEEE 1685-2022 (IP-XACT) e SystemRDL 2.0, migliorando il riutilizzo dell'IP e la compatibilità con terze parti. La piattaforma funge da unica fonte di verità per specificare, documentare, implementare e verificare le mappe degli indirizzi SoC.
Arteris (Nasdaq: AIP) ha anunciado el lanzamiento inmediato de su tecnología de Magillem Registers de próxima generación para la automatización de la integración de SoC. La solución integra los productos Magillem 5 y Semifore CSRCompiler en una plataforma unificada para la gestión de registros y la automatización de la interfaz hardware/software.
Las mejoras clave incluyen hasta 3 veces más velocidad de rendimiento y 5 veces más escalabilidad en comparación con versiones anteriores, apoyando diseños que van desde dispositivos IoT hasta complejos SoC de IA. El producto reduce el tiempo de desarrollo de integración hardware/software en un 35% en comparación con soluciones internas y presenta más de 1,000 verificaciones semánticas y sintácticas para reducir el riesgo de fallos en el silicio.
El lanzamiento amplía el soporte de estándares para incluir IEEE 1685-2022 (IP-XACT) y SystemRDL 2.0, mejorando la reutilización de IP y la compatibilidad con terceros. La plataforma actúa como una única fuente de verdad para especificar, documentar, implementar y verificar los mapas de direcciones de SoC.
Arteris (Nasdaq: AIP)는 SoC 통합 자동화를 위한 차세대 Magillem Registers 기술의 즉각적인 출시를 발표했습니다. 이 솔루션은 Magillem 5와 Semifore CSRCompiler 제품을 통합하여 레지스터 관리 및 하드웨어/소프트웨어 인터페이스 자동화를 위한 통합 플랫폼을 제공합니다.
주요 개선 사항으로는 최대 3배 빠른 성능과 5배 향상된 확장성이 있으며, 이는 IoT 장치에서 복잡한 AI SoC에 이르는 설계를 지원합니다. 이 제품은 내부 솔루션에 비해 하드웨어/소프트웨어 통합 개발 시간을 35% 줄이며, 실리콘 실패 위험을 줄이기 위해 1,000개 이상의 의미론적 및 구문적 검사를 제공합니다.
이번 출시로 IEEE 1685-2022 (IP-XACT) 및 SystemRDL 2.0에 대한 표준 지원이 확대되어 IP 재사용 및 제3자 호환성이 향상됩니다. 이 플랫폼은 SoC 주소 맵을 지정하고 문서화하며 구현하고 검증하기 위한 단일 진실의 원천 역할을 합니다.
Arteris (Nasdaq: AIP) a annoncé le lancement immédiat de sa technologie de Magillem Registers de nouvelle génération pour l'automatisation de l'intégration SoC. La solution intègre les produits Magillem 5 et Semifore CSRCompiler dans une plateforme unifiée pour la gestion des registres et l'automatisation de l'interface matériel/logiciel.
Les améliorations clés incluent jusqu'à 3 fois plus de performances et 5 fois plus d'évolutivité par rapport aux versions précédentes, prenant en charge des conceptions allant des dispositifs IoT aux SoC AI complexes. Le produit réduit le temps de développement de l'intégration matériel/logiciel de 35% par rapport aux solutions internes et propose plus de 1 000 vérifications sémantiques et syntaxiques pour réduire le risque de défaillance du silicium.
La publication élargit le support des normes pour inclure IEEE 1685-2022 (IP-XACT) et SystemRDL 2.0, améliorant la réutilisation de l'IP et la compatibilité avec les tiers. La plateforme sert de source unique de vérité pour spécifier, documenter, mettre en œuvre et vérifier les cartes d'adresses SoC.
Arteris (Nasdaq: AIP) hat die sofortige Einführung seiner nächsten Generation von Magillem Registers Technologie zur Automatisierung der SoC-Integration bekannt gegeben. Die Lösung integriert die Produkte Magillem 5 und Semifore CSRCompiler in eine einheitliche Plattform für das Registermanagement und die Automatisierung der Hardware-/Software-Schnittstelle.
Wesentliche Verbesserungen umfassen bis zu 3x schnellere Leistung und 5x erhöhte Skalierbarkeit im Vergleich zu früheren Versionen, die Designs von IoT-Geräten bis hin zu komplexen AI-SoCs unterstützen. Das Produkt verkürzt die Entwicklungszeit für die Hardware-/Software-Integration um 35% im Vergleich zu internen Lösungen und bietet über 1.000 semantische und syntaktische Prüfungen zur Reduzierung des Risikos von Siliziumausfällen.
Die Veröffentlichung erweitert die Unterstützung von Standards um IEEE 1685-2022 (IP-XACT) und SystemRDL 2.0, was die Wiederverwendbarkeit von IP und die Kompatibilität mit Dritten verbessert. Die Plattform dient als einzige Quelle der Wahrheit für die Spezifizierung, Dokumentation, Implementierung und Verifizierung von SoC-Adressen.
- 35% reduction in hardware/software integration development time
- 3x performance improvement in register compilation speed
- 5x increase in supported design size capacity
- Over 1,000 quality checks to reduce silicon failure risk
- None.
Insights
Arteris's latest Magillem Registers release represents a strategic enhancement to their system IP portfolio that addresses critical pain points in the increasingly complex semiconductor design process. By integrating their acquired Magillem 5 and Semifore CSRCompiler technologies, Arteris has created a unified register management solution that could strengthen their competitive position in the growing $5+ billion EDA market.
The claimed 35% reduction in hardware/software interface development time directly targets one of the most expensive and error-prone aspects of chip design. With over 70% of chips requiring respins according to the company, even incremental improvements in first-time-right success rates can translate to millions in saved development costs for customers. The 3x performance improvement and 5x scalability increase are particularly relevant for addressing the exponential growth in register complexity driven by AI accelerators and heterogeneous computing architectures.
This release strategically positions Arteris to capitalize on three major industry trends:
- The shift toward chiplet-based architectures, which increases the need for robust register management across die boundaries
- The proliferation of AI-enabled SoCs with substantially higher register counts and complexity
- Growing pressure to reduce development costs amid tightening semiconductor industry margins
From a competitive standpoint, Arteris faces established EDA giants like Synopsys and Cadence, but their specialized focus on system IP and integration automation creates a differentiated market position. The expanded standards support (IEEE 1685-2022 and SystemRDL 2.0) enhances interoperability with third-party tools, potentially lowering adoption barriers.
For investors, this product enhancement likely won't drive immediate significant revenue growth, as EDA tool adoption cycles are typically lengthy. However, it strengthens Arteris's overall value proposition and could improve customer retention and expansion opportunities. With a market cap of $386M, Arteris remains a specialized player in the semiconductor ecosystem whose growth is tied to increasing system complexity and integration challenges.
The key risk to monitor is whether the performance and productivity improvements will translate to meaningful customer adoption in a market where switching costs for design tools remain high. Additionally, as a smaller EDA vendor, Arteris must continue demonstrating differentiated value against larger competitors with more comprehensive tool portfolios.
Highlights:
- Solution Integration: Integration of acquired silicon-proven Magillem 5 and Semifore CSRCompiler products into a next-generation ‘single source of truth’ software product for register management and Hardware/Software Interface automation.
- Any Design: Up to 3x expanded performance and 5x scalability address today’s SoCs and FPGA designs, ranging from simple IoT devices to state-of-the-art complex AI SoCs.
- Broad Standards Support: Augments existing support of IEEE 1685-2009 (IP-XACT) standard with support of the 2014 and 2022 versions, and that of Accellera SystemRDL standard with SystemRDL 2.0 for better hardware/software integration.
CAMPBELL, Calif., Feb. 25, 2025 (GLOBE NEWSWIRE) -- Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced the immediate availability of the latest generation of Magillem Registers technology for SoC integration automation. This product enables design teams to automate the hardware/software integration process, reducing the development time by
Magillem Registers is a comprehensive register design and management product that accurately automates the hardware/software interface (HSI) to quickly develop chips and chiplets ranging from IoT devices to complex AI datacenter multi-die SoCs. This product empowers chip architects, hardware designers, firmware engineers, verification teams, and documentation teams to overcome complexity and satisfy the need for real-time, effective cross-functional team communication. It mitigates the risk of out-of-date standards with a unified specification and compilation flow to generate accurate designs.
Building upon the silicon-proven Magillem 5 and CSRCompiler technologies, the latest release of Magillem Registers is designed to streamline and optimize workflows by providing an integrated, single source of truth infrastructure to specify, document, implement, and verify SoC address maps. This approach boosts productivity by promoting efficient IP reuse and ensuring consistency across the relevant design teams. With over 1,000 semantic and syntactic checks, Magillem Registers ensures high-quality output, validating third-party IPs, in-house IPs, and overall system integration to significantly reduce the risk of silicon failure. Additionally, intelligent automation enables a remarkable
The latest release of Magillem Registers brings significant advancements to performance, capacity, standards support, and usability. It delivers up to 3x faster performance compared to Magillem 5, enabling the compilation of millions of registers within minutes while auto-generating synthesizable RTL register banks. With a 5x increase in supported design size, it scales seamlessly from small to very large multi-die devices which contain millions of control registers.
Magillem Registers offers broad support for industry standards, including the addition of IEEE 1685-2022 (IP-XACT) and SystemRDL 2.0, alongside the previous versions. This enhances intellectual property (IP) reuse, and expands compatibility with third-party IP vendors, improving SoC integration. Usability enhancements further boost team productivity with a rapid, highly iterative design environment incorporating features for streamlined input, intuitive document navigation, customizable workflows, and the elimination of repetitive time-consuming and error-prone manual tasks through advanced automation. Magillem Registers addresses the growing demands of modern design environments with unmatched efficiency and scalability.
“With over
Arteris’ SoC integration automation products, including Magillem Registers, are designed to automate around complexity, liberate team productivity, and accelerate quality chiplet and SoC design flows. For more information please visit arteris.com/magillem-registers.
About Arteris
Arteris is a leading provider of system IP for accelerating system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next. Learn more at arteris.com.
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Media Contact:
Gina Jacobs
Arteris
+1 408 560 3044
newsroom@arteris.com
A video accompanying this announcement is available at: https://www.globenewswire.com/NewsRoom/AttachmentNg/d830404f-e4ca-47eb-aaab-14361938bfeb
This press release was published by a CLEAR® Verified individual.
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