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AMD Announces Production Ramp of Next-Generation AMD EPYC Processor “Venice” on TSMC 2nm Process Technology

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AMD (NASDAQ: AMD) announced the production ramp of its 6th Gen AMD EPYC “Venice” CPUs on TSMC’s 2nm process technology in Taiwan, with plans to ramp at TSMC Arizona. “Venice” is described as the first HPC product on TSMC 2nm, targeting cloud, enterprise and AI infrastructure.

AMD also plans a 2nm follow-on CPU, “Verano”, optimized for performance-per-dollar-per-watt and featuring LPDDR support to address growing memory demand in agentic AI workloads, leveraging TSMC’s advanced packaging technologies.

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AI-generated analysis. Not financial advice.

Positive

  • 6th Gen AMD EPYC “Venice” CPUs ramping production on TSMC 2nm
  • “Venice” positioned as first HPC product on TSMC advanced 2nm node
  • Planned additional production ramp of “Venice” at TSMC Arizona fab
  • Roadmap extension with 2nm “Verano” optimized for performance-per-dollar-per-watt
  • “Verano” to integrate LPDDR for higher memory bandwidth in AI workloads
  • Deep AMD–TSMC collaboration including SoIC-X and CoWoS-L packaging

Negative

  • None.

News Market Reaction – AMD

+0.45%
21 alerts
+0.45% News Effect
+2.8% Peak in 6 min
+$3.51B Valuation Impact
$784.34B Market Cap
0.1x Rel. Volume

On the day this news was published, AMD gained 0.45%, reflecting a mild positive market reaction. Argus tracked a peak move of +2.8% during that session. Our momentum scanner triggered 21 alerts that day, indicating elevated trading interest and price volatility. This price movement added approximately $3.51B to the company's valuation, bringing the market cap to $784.34B at that time.

Data tracked by StockTitan Argus on the day of publication.

Key Figures

CPU generation: 6th Gen AMD EPYC Process node: 2nm process technology
2 metrics
CPU generation 6th Gen AMD EPYC Next-generation EPYC CPUs codenamed “Venice”
Process node 2nm process technology TSMC advanced 2nm used for “Venice” and “Verano”

Market Reality Check

Price: $467.60 Vol: Volume 34,767,452 is belo...
normal vol
$467.60 Last Close
Volume Volume 34,767,452 is below the 20-day average of 45,564,710, suggesting an 8.1% move on less-than-typical activity. normal
Technical Price at $447.58 is trading above the 200-day MA of $227.98 and 4.6% below the 52-week high.

Peers on Argus

AMD gained 8.1% while peers were mixed: ARM up 13.33%, QCOM up 2.82%, AVGO up 1....

AMD gained 8.1% while peers were mixed: ARM up 13.33%, QCOM up 2.82%, AVGO up 1.17%, but MU and TXN slightly negative. The move appears stock-specific around the 2nm EPYC ramp news.

Historical Context

5 past events · Latest: May 07 (Neutral)
Pattern 5 events
Date Event Sentiment Move Catalyst
May 07 Annual meeting notice Neutral +11.4% Announcement of 2026 virtual Annual Meeting and voting logistics.
May 05 Earnings results Positive +18.6% Q1 2026 beat with strong data center revenue and higher Q2 outlook.
May 04 AI partnership Positive -5.3% Zyphra Cloud launch powered by AMD Instinct MI355X GPUs.
Apr 28 AI event announcement Positive -3.4% Announcement of Advancing AI 2026 flagship event in July.
Apr 08 Earnings date set Neutral +2.1% Scheduling of Q1 2026 earnings release and investor conference talk.
Pattern Detected

Recent AMD news, especially around earnings and AI/data center themes, has often coincided with double-digit upside moves, though some partnership and event announcements have seen negative follow-through.

Recent Company History

Over the last few months, AMD news has centered on AI, data center growth, and shareholder events. Q1 2026 results on May 5 showed strong revenue and data center growth and coincided with a 18.61% rise. An AI-focused event announcement on April 28 and a Zyphra AI partnership on May 4 both saw modest declines despite constructive narratives. The upcoming 2026 Annual Meeting announcement on May 7 aligned with an 11.44% gain. Today’s 2nm EPYC “Venice” ramp fits the ongoing AI and data center expansion storyline.

Market Pulse Summary

This announcement highlights AMD’s progression to 6th Gen EPYC “Venice” CPUs on TSMC’s advanced 2nm ...
Analysis

This announcement highlights AMD’s progression to 6th Gen EPYC “Venice” CPUs on TSMC’s advanced 2nm process, positioning its data center roadmap for high-performance and AI workloads. The company emphasizes agentic AI use cases and advanced packaging such as SoIC-X and CoWoS-L, alongside future “Verano” CPUs with LPDDR integration. Recent history features strong data center-driven earnings and multiple AI-focused events and partnerships, so investors may watch for how 2nm ramp timing translates into revenue and margin trends.

Key Terms

2nm process technology, high-performance computing (HPC), lpddr, agentic ai workloads, +2 more
6 terms
2nm process technology technical
"production ramp of its 6th Gen AMD EPYC CPUs... on TSMC’s advanced 2nm process technology"
2nm process technology describes a semiconductor manufacturing node where the tiny switches (transistors) on a chip are made at roughly two-nanometer scale, allowing more of them to fit in the same area. For investors it matters because smaller transistors can boost speed and energy efficiency or lower cost per chip, but achieving them requires huge research, specialized factories and higher technical risk that affect profits and capital spending.
high-performance computing (HPC) technical
"“Venice” is the first high-performance computing (HPC) product in the industry"
High-performance computing (HPC) involves using powerful computers to process complex data and run large-scale calculations much faster than regular computers. It helps organizations solve challenging problems, such as predicting market trends or analyzing scientific data, enabling quicker decision-making. For investors, HPC can highlight advancements in technology and innovation that may impact various industries and market opportunities.
lpddr technical
"“Verano” ... with industry leading integration of LPDDR for growing memory demand"
LPDDR (Low-Power Double Data Rate) is a kind of computer memory built for phones, tablets and other battery-powered devices, offering fast data access while consuming less energy than standard memory. Investors monitor LPDDR because its efficiency and performance influence device battery life, manufacturing cost and component demand—traits that can affect product competitiveness, sales volume and supplier profit margins, much like a fuel-efficient engine improves a car’s appeal and running costs.
agentic ai workloads technical
"as agentic AI workloads drive demand for accelerated AI infrastructure deployments"
Agentic AI workloads are computing tasks run by AI systems designed to act autonomously, set or pursue goals, and make sequences of decisions with little human direction — think of software that behaves like a self-directed employee carrying out complex projects. Investors care because these workloads can change cost structures (more compute and data use), accelerate automation and product capabilities, and introduce new operational, safety and regulatory risks that can materially affect a company’s growth and valuation.
soic®-x technical
"advanced packaging technologies, including TSMC’s SoIC®-X and CoWoS®-L"
soic®-x is a trademarked name for a proprietary medical or biotech product or technology platform, typically used for diagnostics, treatment or a related clinical purpose. Investors care because its commercial value depends on clinical results, regulatory approvals, manufacturing scale and payment by health systems — like a new, expensive tool that can replace older ones: if it works and is approved it can drive sales and margins, but setbacks in testing or regulation can sharply reduce its market value.
cowoS®-l technical
"advanced packaging technologies, including TSMC’s SoIC®-X and CoWoS®-L"
cowos®-l is a proprietary multi-chip packaging technology that places and electrically links several separate silicon chip components within a single package to act like one larger chip. Think of it as tightly fitting puzzle pieces connected with very short wiring so data moves faster and uses less power than across traditional circuit board traces. Investors watch this because it can significantly boost product performance and density, influence manufacturing cost and complexity, and affect competitive advantage in high-performance electronics.

AI-generated analysis. Not financial advice.

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News Summary:

  • AMD has begun production ramp of its 6th Gen AMD EPYC™ CPUs, codenamed “Venice,” marking a major milestone for the AMD and TSMC collaboration on 2nm technology
  • “Venice” is the first HPC product in the industry to achieve production ramp on TSMC advanced 2nm technology
  • Critical milestone achieved as agentic AI workloads drive demand for accelerated AI infrastructure deployments
  • AMD continues to drive 2nm product expansion with “Verano” a follow on to “Venice” with industry leading integration of LPDDR for growing memory demand in agentic AI workloads

SANTA CLARA, Calif., May 21, 2026 (GLOBE NEWSWIRE) -- AMD (NASDAQ: AMD) today announced that its next-generation AMD EPYC™ processor, codenamed “Venice,” is ramping production in Taiwan on TSMC’s advanced 2nm process technology, with future plans to ramp production at TSMC’s Arizona fabrication facility. The milestone in the execution of the AMD data center CPU roadmap demonstrates continued progress toward delivering the leadership performance and energy efficiency required for next-generation cloud, enterprise and AI infrastructure. “Venice” is the first high-performance computing (HPC) product in the industry to enter production on TSMC’s advanced 2nm process technology.

“Ramping ‘Venice’ on TSMC 2nm process technology marks an important step forward in accelerating the next generation of AI infrastructure,” said Dr. Lisa Su, chair and CEO, AMD. “As AI and agentic workloads scale rapidly, customers need platforms that can move from innovation to production faster. Our deep partnership with TSMC is helping AMD bring leadership compute technologies to market with the speed and scale required to meet this moment.”

As AI adoption expands from training and inference to increasingly complex agentic workloads, the CPU is becoming even more critical to scaling AI infrastructure, coordinating data movement, networking, storage, security and system orchestration across the data center. The ramp of “Venice” comes as AMD continues to build momentum in the server market, reflecting growing customer demand for EPYC processors to power modern cloud, enterprise, HPC and AI deployments.

The “Venice” ramp in Taiwan and plans to ramp at TSMC Arizona reflect AMD’s focus on strengthening its geographically diverse advanced manufacturing footprint. By pairing next-generation EPYC processor innovation with advanced manufacturing capacity across the globe, AMD is expanding the foundation needed to support customers as they deploy and scale AI infrastructure.

“We are pleased to see AMD continue to make strong progress with its next-generation EPYC processor on our advanced 2nm process technology,” said Dr. C.C. Wei, Chairman and CEO, TSMC. “Our close collaboration with AMD reflects the importance of pairing leadership process technology with advanced design innovation to enable the next era of high-performance and AI computing.”

AMD also plans to extend TSMC 2nm process technology across its data center CPU roadmap with “Verano,” a 6th Gen EPYC processor optimized for performance-per-dollar-per-watt leadership. Designed to support cloud and AI computing workloads, “Verano” is expected to build on the AMD EPYC platform with advanced memory innovations, including LPDDR, to deliver the CPU performance, bandwidth and efficiency required for increasingly power constrained workloads and applications.

AMD and TSMC’s partnership spans the technologies needed to scale modern data center computing, from TSMC 2nm process technology for next-generation CPUs to advanced packaging technologies, including TSMC’s SoIC®-X and CoWoS®-L, used across AMD’s broader AI and data center portfolio. With “Venice” ramping on TSMC 2nm, AMD is advancing the CPU foundation for AI infrastructure while continuing to leverage TSMC’s process and packaging leadership to deliver increasingly integrated compute platforms at scale.

About AMD

AMD (NASDAQ: AMD) drives innovation in high-performance and AI computing to solve the world’s most important challenges. Today, AMD technology powers billions of experiences across cloud and AI infrastructure, embedded systems, AI PCs and gaming. With a broad portfolio of AI-optimized CPUs, GPUs, networking and software, AMD delivers full-stack AI solutions that provide the performance and scalability needed for a new era of intelligent computing. Learn more at www.amd.com.

Cautionary Statement

This press release contains forward-looking statements concerning Advanced Micro Devices, Inc. (AMD) such as the ramping of AMD’s 6th Gen AMD EPYC™ CPUs and future plans and expectations of its partnership with TSMC, which are made pursuant to the Safe Harbor provisions of the Private Securities Litigation Reform Act of 1995. Forward-looking statements are commonly identified by words such as "would," "may," "expects," "believes," "plans," "intends," "projects" and other terms with similar meaning. Investors are cautioned that the forward-looking statements in this press release are based on current beliefs, assumptions and expectations, speak only as of the date of this press release and involve risks and uncertainties that could cause actual results to differ materially from current expectations. Such statements are subject to certain known and unknown risks and uncertainties, many of which are difficult to predict and are generally beyond AMD's control, that could cause actual results and other future events to differ materially from those expressed in, or implied or projected by, the forward-looking information and statements. Material factors that could cause actual results to differ materially from current expectations include, without limitation, the following: impact of government actions and regulations such as export regulations, import tariffs, trade protection measures, and licensing requirements; competitive markets in which AMD’s products are sold; the cyclical nature of the semiconductor industry; market conditions of the industries in which AMD products are sold; AMD’s ability to introduce products on a timely basis with expected features and performance levels; loss of a significant customer; economic and market uncertainty; quarterly and seasonal sales patterns; AMD's ability to adequately protect its technology or other intellectual property; unfavorable currency exchange rate fluctuations; ability of third party manufacturers to manufacture AMD's products on a timely basis in sufficient quantities and using competitive technologies; availability of essential equipment, materials, components (such as memory supply), substrates or manufacturing processes; ability to achieve expected manufacturing yields for AMD’s products; AMD's ability to generate revenue from its semi-custom SoC products; potential security vulnerabilities; potential security incidents including IT outages, data loss, data breaches and cyberattacks; uncertainties involving the ordering and shipment of AMD’s products; AMD’s reliance on third-party intellectual property to design and introduce new products; AMD's reliance on third-party companies for design, manufacture and supply of motherboards, software, memory and other computer platform components; AMD's reliance on Microsoft and other software vendors' support to design and develop software to run on AMD’s products; AMD’s reliance on third-party distributors and add-in-board partners; impact of modification or interruption of AMD’s internal business processes and information systems; compatibility of AMD’s products with some or all industry-standard software and hardware; costs related to defective products; failure to maintain an efficient supply chain as customer demand changes; AMD's ability to rely on third party supply-chain logistics functions; AMD’s ability to effectively control sales of its products on the gray market; impact of climate change on AMD’s business; AMD’s ability to realize its deferred tax assets; potential tax liabilities; current and future claims and litigation; impact of environmental laws, conflict minerals related provisions and other laws or regulations; evolving expectations from governments, investors, customers and other stakeholders regarding corporate responsibility matters; issues related to the responsible use of AI; restrictions imposed by agreements governing AMD’s notes, the guarantees of Xilinx’s notes and the revolving credit agreement; AMD’s ability to satisfy financial obligations under guarantees, leases and other commercial commitments; impact of acquisitions, joint ventures and/or investments on AMD’s business and AMD’s ability to integrate acquired businesses; impact of any impairment of the combined company’s assets; political, legal and economic risks and natural disasters; future impairments of technology license purchases; AMD’s ability to attract and retain key employees; and AMD’s stock price volatility. Investors are urged to review in detail the risks and uncertainties in AMD’s Securities and Exchange Commission filings, including but not limited to AMD’s most recent reports on Forms 10-K and 10-Q.

Media Contact:
Phil Hughes
AMD Communications
512-865-9697
phil.hughes@amd.com
        
Investor Contact:
Liz Stine
AMD Investor Relations
720-652-3965
liz.stine@amd.com


FAQ

What did AMD (NASDAQ: AMD) announce about its 6th Gen EPYC “Venice” CPUs on May 21, 2026?

AMD announced that 6th Gen EPYC “Venice” CPUs are ramping production on TSMC’s advanced 2nm process technology. According to AMD, this milestone supports next-generation cloud, enterprise and AI infrastructure, with production in Taiwan and future plans to ramp at TSMC’s Arizona facility.

Why is AMD’s EPYC “Venice” production ramp on TSMC 2nm technology significant for AI infrastructure?

The “Venice” ramp on TSMC 2nm is presented as a key step for scaling AI infrastructure. According to AMD, CPUs coordinate data movement, networking, storage, security and orchestration for complex agentic AI workloads, making advanced process technology important for performance and energy efficiency.

How does the AMD EPYC “Venice” 2nm ramp involve TSMC’s Arizona fabrication facility?

AMD plans to follow the Taiwan production ramp of EPYC “Venice” with additional ramp at TSMC’s Arizona fab. According to AMD, this approach supports a geographically diverse advanced manufacturing footprint to help customers deploy and scale AI, cloud and enterprise infrastructure globally.

What is AMD’s upcoming 6th Gen EPYC “Verano” processor and how will it use TSMC 2nm?

“Verano” is a planned 6th Gen EPYC CPU using TSMC 2nm, optimized for performance-per-dollar-per-watt. According to AMD, it targets cloud and AI computing workloads and will add advanced memory innovations, including LPDDR, to improve CPU performance, bandwidth and efficiency for power-constrained applications.

How will AMD EPYC “Verano” with LPDDR support address AI and cloud memory needs for AMD stock investors?

EPYC “Verano” is expected to integrate LPDDR to meet rising memory demand in agentic AI and cloud workloads. According to AMD, these memory innovations aim to deliver the bandwidth and efficiency required by increasingly power-constrained data center applications, extending the EPYC platform’s capabilities.

What role does TSMC play in AMD’s 2nm EPYC “Venice” and “Verano” roadmap?

TSMC provides 2nm process technology and advanced packaging for AMD’s next-generation EPYC CPUs. According to AMD, the partnership spans 2nm manufacturing plus SoIC-X and CoWoS-L packaging, helping deliver highly integrated compute platforms across AI, data center, cloud and high-performance computing markets.

How does AMD describe the impact of EPYC “Venice” on the server and AI markets?

AMD links the “Venice” ramp to growing server momentum and demand for EPYC in cloud, enterprise, HPC and AI. According to AMD, the CPU’s role in coordinating complex agentic AI workloads makes 2nm-based EPYC a foundation for future AI infrastructure deployments.