AMD Extends Market-Leading FPGA Portfolio with AMD Spartan UltraScale+ Family Built for Cost-Sensitive Edge Applications
AMD introduces the Spartan UltraScale+ FPGA family, offering high I/O counts, power efficiency, and advanced security features for various applications. The new FPGAs provide industry-leading I/O to logic cell ratio, up to 30% lower power consumption, and robust security features. The family is optimized for edge applications, with flexible I/O interfacing and power-efficient compute capabilities. AMD emphasizes security with features like Post-Quantum Cryptography and physical unclonable function. The Spartan UltraScale+ FPGAs are supported by the AMD Vivado Design Suite and Vitis Unified Software Platform, enhancing design productivity.
The announcement of AMD's Spartan UltraScale+ FPGA family represents a significant advancement in the semiconductor industry, particularly for edge computing applications. The introduction of FPGAs with high I/O counts and power efficiency is critical as the demand for processing at the edge increases, driven by the proliferation of IoT devices and the need for real-time data processing.
The reduction in power consumption by up to 30 percent is a noteworthy achievement, as it not only lowers operational costs for users but also aligns with the industry's push towards sustainability. Additionally, the Spartan UltraScale+ family's high I/O to logic cell ratio is particularly relevant for applications such as embedded vision and healthcare, where high data throughput and connectivity are essential.
From an investment perspective, this launch could position AMD as a more competitive player in the FPGA market, potentially capturing market share from rivals and driving revenue growth. However, it's important to note that the full financial impact will depend on the adoption rate of these new FPGAs and AMD's ability to scale production effectively.
The state-of-the-art security features integrated into the Spartan UltraScale+ FPGAs are a testament to the growing importance of cybersecurity in the semiconductor space. The inclusion of Post-Quantum Cryptography is particularly forward-looking, as it anticipates future threats associated with quantum computing.
For industries like healthcare and industrial networking, where data security is paramount, these features may provide a competitive advantage for AMD. The physical unclonable function and enhanced single-event upset performance also demonstrate AMD's commitment to robust security, which is crucial for maintaining the integrity of edge computing networks.
While these security advancements are impressive, it's essential to monitor how they perform in real-world scenarios once the FPGAs are deployed. Security features can also be a double-edged sword if not implemented correctly, potentially introducing new vulnerabilities or complexities.
The technical specifications of the Spartan UltraScale+ FPGA family suggest a strong focus on flexible I/O interfacing and power-efficient compute , which are vital for modern electronics design. The ability to support any-to-any connectivity with high I/O density in a compact footprint is particularly appealing for space-constrained applications such as robotics and portable medical devices.
The shift to 16nm FinFET technology and the inclusion of a hardened LPDDR5 memory controller and PCIe Gen4 x8 support are indicative of AMD's strategy to offer high-performance yet power-efficient solutions. These features not only provide immediate benefits in terms of energy savings and performance but also ensure that the products remain relevant as technology standards evolve.
For businesses and developers, the compatibility with the AMD Vivado Design Suite and Vitis Unified Software Platform can streamline the design process, potentially reducing time-to-market for new products. However, the true test will be in the adoption rate by the engineering community and the ease with which they can integrate these FPGAs into their existing systems.
03/05/2024 - 09:00 AM
— New FPGAs offer high I/O counts, power efficiency, and state-of-the-art security features for embedded vision, healthcare, industrial networking, robotics, and video applications —
SANTA CLARA, Calif., March 05, 2024 (GLOBE NEWSWIRE) -- AMD AMD Spartan™ UltraScale+™ FPGA family , the newest addition to the extensive portfolio of AMD Cost-Optimized FPGAs and adaptive SoCs. Delivering cost and power-efficient performance for a wide range of I/O-intensive applications at the edge, Spartan UltraScale+ devices offer the industry’s highest I/O to logic cell ratio in FPGAs built in 28nm and lower process technologyi , deliver up to 30 percent lower total power consumption versus the previous generationii , and contain the most robust set of security featuresiii in the AMD Cost-Optimized Portfolio .
“For over 25 years the Spartan FPGA family has helped power some of humanity’s finest achievements, from lifesaving automated defibrillators to the CERN particle accelerator advancing the boundaries of human knowledge,” said Kirk Saban, corporate vice president, Adaptive and Embedded Computing Group, AMD. “Building on proven 16nm technology, the Spartan UltraScale+ family’s enhanced security and features, common design tools, and long product lifecycles further strengthen our market-leading FPGA portfolio and underscore our commitment to delivering cost-optimized products for customers.”
Flexible I/O Interfacing and Power Efficient Compute
The family offers the industry’s highest I/O to logic cell ratio of FPGAs built on 28nm and below process technology, with up to 572 I/Os and voltage support up to 3.3V, enabling any-to-any connectivity for edge sensing and control applications. The proven 16nm fabric and support for a wide array of packaging, starting as small as 10x10mm, provide high I/O density in an ultra-compact footprint. The extensive AMD FPGA portfolio also provides the scalability to start with cost-optimized FPGAs and continue through to midrange and high-end products.
The Spartan UltraScale+ family is estimated to offer up to a 30 percent reduction in power compared to the 28nm Artix™ 7 family, through 16nm FinFET technology and hardened connectivity. They are the first AMD UltraScale+ FPGAs with a hardened LPDDR5 memory controller and PCIe® Gen4 x8 support, providing both power efficiency and future-ready capabilities for customers.
State-of-the-Art Security Features
Protecting IP: Support for Post-Quantum Cryptography with NIST-approved algorithms offers state-of-the-art IP protection against evolving cyber-attacks and threats. A physical unclonable function provides each device with a unique fingerprint for added security. Preventing tampering: PPK/SPK key support helps manage obsolete or compromised security keys while differential power analysis helps protect against side-channel attacks. The devices contain a permanent tamper penalty to further protect against misuse. Maximizing uptime: Enhanced single-event upset performance helps fast and secure configuration with increased reliability for customers. The entire AMD portfolio of FPGAs and adaptive SoCs are supported by the AMD Vivado™ Design Suite and Vitis™ Unified Software Platform, allowing hardware and software designers to leverage the productivity benefits of these tools and included IPs via a single designer cockpit from design to verification.
AMD Spartan UltraScale+ FPGA family sampling and evaluation kits are expected to be available in the first half of 2025. Documentation is available today with tools support starting with the AMD Vivado Design Suite in the fourth quarter of 2024.
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©2024 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo, Artix, Spartan, UltraScale+, Vitis, Vivado, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other names used herein are for informational purposes only and may be trademarks of their respective owners.
i Based on product datasheets for AMD Spartan™ UltraScale+™ FPGAs and published datasheets for Efinix, Intel, Lattice, and Microchip as of February 2024, comparing the total I/O to logic cell ratios of comparable 28nm and lower node size FPGAs. (SUS-11)
ii Projection is based on an AMD Labs internal analysis in January 2024, using total power calculation (static plus dynamic power) based on the difference in logic cell count of an AMD Artix™ UltraScale+ AU7P FPGA, to estimate the power of a 16nm AMD Spartan™ UltraScale+™ SU35P FPGA, versus a 28nm AMD Artix 7 7A35T FPGA, using Xilinx Power Estimator (XPE) tool version 2023.1.2. Total power may vary when products are released in market and based on configuration, usage, and other factors. (SUS-03)
iii Based on AMD internal analysis in December 2023, using the product datasheets to compare the number of security features in Spartan™ UltraScale+™ FPGAs to previous generation AMD cost-optimized FPGAs. (SUS-02)
iv Revenue data, Omdia Competitive Landscape Tool CTL, Quarterly Semiconductor Market Share. November 2023.
Contact: Mike Sanchez M.Sanchez@amd.com
Suresh Bhaskaran Suresh.Bhaskaran@amd.com
A photo accompanying this announcement is available at https://www.globenewswire.com/NewsRoom/AttachmentNg/7a0338aa-8711-4a93-b16b-f699f5f0eb3c
AMD announced the Spartan UltraScale+ FPGA family.
The FPGAs offer high I/O counts, power efficiency, and advanced security features.
The FPGAs provide the industry's highest I/O to logic cell ratio in FPGAs built on 28nm and below process technology.
The FPGAs deliver up to 30% lower total power consumption versus the previous generation.
The FPGAs offer state-of-the-art security features like Post-Quantum Cryptography and physical unclonable function.
