Cadence Design System Inc Stock Price, News & Analysis

Cadence Design Systems (NASDAQ: CDNS) has announced that Senior Vice President and CFO John Wall will participate in a fireside chat at the BofA Securities 2025 Global Technology Conference. The presentation is scheduled for Tuesday, June 3, 2025, at 10:00 a.m. PDT.

The event will be accessible via live webcast on the company's website, and the recording will remain available for replay for 180 days through Cadence's investor relations page at cadence.com/cadence/investor_relations.

Cadence (CDNS) has unveiled the Tensilica NeuroEdge 130 AI Co-Processor (AICP), a new processor designed to complement neural processing units (NPUs) for AI applications. The processor delivers 30% area savings and over 20% reduction in dynamic power and energy while maintaining performance levels. The NeuroEdge 130 AICP features an extensible design compatible with various NPUs and is supported by the NeuroWeave Software Development Kit.

The processor is specifically designed for end-to-end execution of agentic and physical AI networks in automotive, consumer, industrial, and mobile SoCs. It includes VLIW-based SIMD architecture with configurable options and optimized ISA for non-NPU tasks. The product is currently available and is ISO 26262-ready for automotive applications.

Cadence Design Systems (NASDAQ: CDNS) has announced that Nimish Modi, Senior Vice President and General Manager of Strategy & New Ventures, will participate in a virtual fireside chat at the 20th Annual Needham Technology, Media, & Consumer Conference. The presentation is scheduled for Monday, May 12, 2025, at 10:30 a.m. PDT. Investors and interested parties can access the live webcast through Cadence's website, and the presentation will remain available for replay for 90 days following the event.

Cadence has significantly expanded its design IP portfolio optimized for Intel 18A and Intel 18A-P technologies, focusing on advancing AI, HPC, and mobility applications. The collaboration includes:

• New IP additions including 224G SerDes, DDR5-12.8G, and UCIe 1.1 48G for chiplet architectures
• AI-driven digital and analog/custom design solutions certified for Intel 18A PDK
• Advanced packaging workflow development using Intel's EMIB-T technology

As a founding member of the Intel Foundry Chiplet Alliance, Cadence is strengthening its partnership with Intel Foundry to deliver optimized power, performance, and area efficiencies. The expanded portfolio leverages RibbonFET Gate-all-around transistors and PowerVia backside power delivery network, enabling customers to accelerate time-to-market for cutting-edge system-on-chip designs.

Cadence reported strong Q1 2025 financial results, with revenue reaching $1.242 billion, up 23% year-over-year. The company's non-GAAP earnings per share increased 34% to $1.57.

Key financial highlights:

• GAAP operating margin improved to 29.1% from 24.8% in Q1 2024
• Quarter-end backlog reached $6.4 billion
• Current remaining performance obligations stood at $3.2 billion

The company raised its 2025 outlook, now expecting:

• Revenue between $5.15-5.23 billion
• Non-GAAP EPS of $6.73-6.83

Business performance was strong across segments, with Semiconductor IP revenue growing 40% and Core EDA revenue up 16%. The AI-driven Cadence Cerebrus platform gained nearly 50 new customers in Q1. The company expanded its partnership with NVIDIA and saw over 50% growth in System Design and Analysis revenue.

Cadence (CDNS) has strengthened its partnership with TSMC to accelerate 3D-IC and advanced-node technology development through certified design flows and silicon-proven IP. The collaboration includes certification for TSMC's N2P and A16 technologies, with initial work on A14 technology.

Key developments include:

• TSMC9000 pre-silicon-certified DDR5 12.8G IP for N2P
• Certified IP for TSMC's N5A and N3A processes targeting automotive applications
• Expansion of design IP portfolio with HBM3E 9.6G in N5/N4P and pre-silicon HBM3E 10.4G in N3P
• Enhanced Integrity 3D-IC Platform with improved quality of results and 3DIC full flow QC

The partnership focuses on AI chip design innovation, automotive solutions for ADAS and autonomous driving, and advancement in 3DFabric solutions for chiplet design and packaging.

Cadence (CDNS) has unveiled the industry's first DDR5 12.8Gbps MRDIMM Gen2 memory IP system solution on TSMC N3 process, targeting enterprise and data center applications with AI processing demands. The solution features a doubled bandwidth compared to current DDR5 6400Mbps DRAM parts.

The new memory IP system includes a PHY and high-performance controller, offering ultra-low latency encryption and advanced RAS features. The solution has been validated in hardware using the latest Gen2 MRDIMMs and is designed to enable advanced SoCs and chiplets with flexible floorplan options.

The technology has already secured multiple engagements with leading AI, HPC, and data center customers. The solution is compatible with Micron's 1γ-based DRAM and Montage's MRCD02/MDB02 chips for MRDIMMs, positioning it as a key enabler for next-generation server and data center products.

Cadence (CDNS) has unveiled the industry's fastest HBM4 12.8Gbps memory IP solution, designed for next-generation AI training and HPC hardware systems. The solution, compatible with JEDEC specification JESD270-4, doubles the memory bandwidth compared to previous HBM3E IP products.

Key features include:

• 20% greater power efficiency per bit
• 50% better area efficiency
• Double the number of I/Os for higher bandwidth
• 12.8Gbps data rate exceeding HBM4 DRAM device speeds by 60%

The solution includes a PHY available as a drop-in hardened macro in TSMC N3 and N2 technology nodes, and a controller provided as a soft RTL macro. The package includes comprehensive deliverables, reference interposer design, and LabStation software for rapid SoC post-silicon lab bring-up.