MicroCloud Hologram Inc. Utilizes FPGA to Accelerate Tensor Network Computing to Achieve Quantum Spin Models

Rhea-AI Summary

MicroCloud Hologram (NASDAQ: HOLO) on January 16, 2026 announced an FPGA-based hardware acceleration approach that maps tensor network algorithms into parallel logic circuits to simulate quantum spin models on classical hardware.

The company described a Hierarchical Tensor Contraction Pipeline with input/scheduling, core MAC-array compute, and output/reduction layers, claiming a performance improvement of 1.7x vs CPU and energy efficiency improved by more than 2x. HOLO said it holds cash reserves exceeding 3 billion RMB and plans to invest over 400 million USD into blockchain, quantum computing, quantum holography, and related frontier technologies.

Positive

• FPGA acceleration achieves 1.7x speed vs CPU
• Energy efficiency improvement of more than 2x
• Defined Hierarchical Tensor Contraction Pipeline for TN workloads
• Cash reserves exceed 3 billion RMB

Negative

• Plans to deploy >400 million USD from cash reserves may materially consume liquidity
• Performance claims (1.7x, >2x energy) lack detailed benchmarking context in the announcement

News Market Reaction

+1.41%

1 alert

+1.41% News Effect

On the day this news was published, HOLO gained 1.41%, reflecting a mild positive market reaction.

Data tracked by StockTitan Argus on the day of publication.

Key Figures

Entanglement rank low: χ = 8 Entanglement rank high: χ = 32 Performance gain: 1.7 times faster +3 more

6 metrics

Entanglement rank low χ = 8 Two-dimensional spin system baseline entanglement rank example

Entanglement rank high χ = 32 Higher entanglement rank driving sharp complexity growth

Performance gain 1.7 times faster FPGA tensor network acceleration vs CPU performance

Energy efficiency gain More than 2 times FPGA solution energy efficiency improvement vs CPU

Cash reserves Over 3 billion RMB Company cash reserves cited alongside quantum strategy

Planned investment More than 400 million USD Planned spend on blockchain, quantum, holography, AI/AR

Market Reality Check

Price: $2.18 Vol: Volume 507,188 is about i...

normal vol

$2.18 Last Close

Volume Volume 507,188 is about in line with the 20-day average of 613,052 (relative volume 0.83). normal

Technical Price at $2.83 is trading below the 200-day MA of $6.19 and far under the 52-week high of $103.60.

Peers on Argus

HOLO showed a small gain while peers were mixed: notable movers included ELTK up...

1 Down

HOLO showed a small gain while peers were mixed: notable movers included ELTK up 2.77% and NEON up 1.06%, with others flat or down and only 1 peer in the momentum scanner.

Historical Context

5 past events · Latest: Jan 08 (Positive)

Pattern 5 events

Date	Event	Sentiment	Move	Catalyst
Jan 08	Quantum QFT simulator	Positive	+2.0%	Launch of scalable multi-FPGA quantum Fourier transform simulator.
Jan 05	Quantum spectral filter	Positive	+7.9%	Release of learnable quantum spectral filter for hybrid graph neural networks.
Jan 02	Q-DPC accelerator launch	Positive	+4.9%	Introduction of quantum-enhanced density peak clustering accelerator for strategy evaluation.
Dec 22	FPGA sim framework	Positive	+2.7%	Development of serial-parallel FPGA-based quantum computing simulation framework.
Dec 18	Quantum 3D imaging	Positive	-1.4%	Quantum-enhanced deep CNN image 3D reconstruction technology announcement.

Pattern Detected

Recent quantum/FPGA innovation news has often been followed by positive single-day price reactions, with one notable negative divergence.

Recent Company History

Over the past month, MicroCloud Hologram has released multiple quantum and FPGA-focused innovations. On Dec 18, 2025, it announced a quantum-enhanced 3D reconstruction system. Subsequent releases on Dec 22, Jan 2, Jan 5, and Jan 8, 2026 featured FPGA simulation, a Q-DPC accelerator, a quantum spectral filter, and a multi-FPGA QFT simulator. These were paired with repeated disclosures of cash reserves above 3 billion RMB and planned investments over $400 million, reinforcing a consistent quantum-computing strategy leading into today’s tensor-network FPGA update.

Market Pulse Summary

This announcement extends MicroCloud Hologram’s focus on quantum and FPGA technologies by introducin...

Analysis

This announcement extends MicroCloud Hologram’s focus on quantum and FPGA technologies by introducing an FPGA-based acceleration approach for tensor network quantum spin models, claiming a 1.7x performance and over 2x energy-efficiency improvement vs CPU. It complements recent launches in QFT simulation and quantum machine learning. Repeated references to cash reserves above 3 billion RMB and plans to invest more than $400 million into frontier fields highlight ongoing resource allocation to build a broader quantum acceleration ecosystem.

Key Terms

field programmable gate arrays, tensor network, matrix product states, projected entangled pair states, +3 more

7 terms

field programmable gate arrays technical

"run on field programmable gate arrays (FPGA), achieving efficient quantum"

Field programmable gate arrays (FPGAs) are semiconductor chips that can be reconfigured after manufacture to perform different digital tasks, like a box of electronic LEGO that can be rearranged to build new circuits. For investors, FPGAs matter because they let customers update hardware functions without buying new chips, creating demand for flexible, high-performance solutions across data centers, telecom, and specialized devices—impacting companies' revenue streams, product lifecycles, and profit potential.

tensor network technical

"the tensor network (TN) algorithm is an extremely efficient numerical tool"

A tensor network is a way of linking many multidimensional data blocks so a complex system can be represented and computed more efficiently, like snapping together Lego pieces that each store a slice of information. Investors should care because these structures underpin advanced models used for forecasting, risk analysis and pattern detection in large datasets, making some quantitative strategies faster, more scalable and better at capturing subtle relationships.

matrix product states technical

"Typical tensor network models include matrix product states (MPS), projected"

A way to represent the complex state of many interacting quantum bits using a chain of small matrices that capture how parts of the system are correlated, like encoding a long recipe by stacking a few reusable cards instead of writing every step out in full. It matters to investors because this compact representation is a key tool behind quantum computing, advanced materials simulation and some machine‑learning methods, so improvements can lower costs and speed development for companies working on next‑generation computing and diagnostics.

projected entangled pair states technical

"include matrix product states (MPS), projected entangled pair states (PEPS)"

Projected entangled pair states are a mathematical way to describe and simulate how many interacting quantum particles behave together by linking small, simple building blocks into a larger pattern, like assembling a mosaic from tiles that share edges. Investors should care because this approach lets researchers model complex quantum materials and algorithms more efficiently, which can speed development of quantum hardware, new materials and software with commercial or competitive value.

multi-scale entanglement renormalization technical

"and multi-scale entanglement renormalization (MERA), etc."

A method from quantum physics and computing that represents and simulates complex systems by organizing their parts into layers of detail, compressing information step by step much like creating progressively simplified versions of a high-resolution image. For investors, advances in this approach can speed up realistic simulations used in developing new materials, drugs and cryptography, potentially reducing R&D time and costs or enabling new commercial products and risks for companies in computing, pharmaceuticals and cybersecurity.

verilog technical

"through the combined method of Verilog and high-level synthesis (HLS)"

Verilog is a specialized programming language used by engineers to design and simulate electronic circuits and computer chips, acting like a blueprint that describes how hardware should behave. Investors care because mention of Verilog in corporate documents often signals active chip or hardware development, which affects a company’s product timelines, costs, intellectual property and competitive position—similar to seeing architectural plans for a building when judging a construction project's prospects.

high-level synthesis technical

"Verilog and high-level synthesis (HLS) tools, tensor operation circuits"

High-level synthesis is the automated process of turning a software-like description of how a circuit should behave into a detailed hardware blueprint that can be manufactured or loaded onto programmable chips. For investors, it matters because it can speed product development, reduce engineering cost and risk, and improve the chance a company meets performance and time-to-market targets — akin to turning a recipe into a ready-to-build kitchen plan faster and with fewer errors.

AI-generated analysis. Not financial advice.

SHENZHEN, China, Jan. 16, 2026 /PRNewswire/ -- MicroCloud Hologram Inc. (NASDAQ: HOLO), ("HOLO" or the "Company"), a technology service provider, proposed an innovative hardware acceleration technology that converts the quantum tensor network algorithm into parallel computing circuits that can run on field programmable gate arrays (FPGA), achieving efficient quantum spin model simulation on classical hardware. This achievement provides a brand-new engineered path for quantum physics research, quantum algorithm verification, and digital twin simulation of future quantum devices.

In the research of quantum many-body systems, the tensor network (TN) algorithm is an extremely efficient numerical tool. It overcomes the problem of exponential state space expansion to a certain extent by decomposing high-dimensional quantum states into a network structure of multiple low-dimensional tensors. Typical tensor network models include matrix product states (MPS), projected entangled pair states (PEPS), and multi-scale entanglement renormalization (MERA), etc. These algorithms play a foundational role in condensed matter physics, quantum phase transitions, quantum spin model simulations, and other aspects.

However, when we hope to improve the precision of system characterization and introduce higher entanglement degrees of freedom, the dimensions and connectivity of tensors grow sharply, causing the computational complexity to rapidly cross from polynomial to exponential levels. Taking a two-dimensional spin system as an example, when the entanglement rank expands from χ=8 to χ=32, the floating-point operations per iteration increase nearly a hundredfold, and storage bandwidth and memory access latency become bottlenecks. This exponential explosion characteristic makes it difficult even for high-end CPU and GPU platforms to complete simulation tasks within a reasonable time.

To this end, HOLO attempts to break out of the limitations of traditional processor architectures and explore feasible paths for algorithm reconstruction and logic mapping at the hardware level. Field programmable gate arrays (FPGA), with their reconfigurability, parallelism, and low-latency characteristics, provide new possibilities for tensor network computations. By directly mapping core computational modules (such as tensor contraction, tensor unfolding, matrix multiplication-addition operations, etc.) into hardware circuits at the logic level, it can greatly reduce memory access consumption and control overhead, achieving deep pipelined high-density parallel computing.

The core of HOLO's technology lies in algorithm-hardware co-design, which dissects the tensor network algorithm from the software logic level into computational units that can be directly hardware-ized, and builds a high-density parallel scalable architecture with FPGA as the carrier.

First, a systematic analysis was performed on the tensor network structure of quantum spin models. Typical systems represented by the Heisenberg spin chain and the two-dimensional Ising model have their Hamiltonians decomposable into local interaction terms, encoded into several local tensors through tensor networks. The contraction of each tensor node essentially corresponds to tensor product, matrix multiplication, and summation operations. Traditional CPU computations rely on sequential execution of general instruction sets, while GPUs, although possessing large-scale parallelism, are limited by memory access latency and kernel scheduling, making it difficult to achieve targeted optimization. The FPGA architecture allows direct definition of these computational logics at the hardware level, eliminating redundant scheduling links, enabling data to flow continuously in a pipeline manner in the on-chip high-speed cache.

In the implementation, HOLO constructed a Hierarchical Tensor Contraction Pipeline. This pipeline includes three main levels:

Input and scheduling layer: responsible for decomposing high-dimensional tensors into several manageable block structures, and performing data flow scheduling and dependency analysis.

Core computing layer: composed of multiple MAC Array, supporting tensor contraction operations of arbitrary dimensions. Each computing unit adopts customized logic to achieve pipeline-level parallelism for floating-point addition and multiplication.

Output and reduction layer: executes the merging, normalization, and intermediate state caching of tensor results, providing input for subsequent iterations.

In the hardware logic design, through the combined method of Verilog and high-level synthesis (HLS) tools, tensor operation circuits are automatically generated, and multi-partition strategies are adopted for different tensor connectivity graphs. Through static scheduling and data reuse mechanisms, the computing units form a high-density parallel array on-chip, achieving the maximum computational throughput rate under limited logic resources.

This technology takes FPGA as the core hardware platform, proposing and implementing a parallelized hardware architecture for accelerating quantum tensor network computations. Through algorithm structure reconstruction, logic circuit mapping, pipelined design, and mixed-precision optimization, HOLO successfully transforms complex tensor network computational tasks into efficient FPGA logic operations, achieving a performance breakthrough that is 1.7 times faster than CPU and with energy efficiency improved by more than 2 times. This technology not only demonstrates the potential of FPGA in quantum simulation but also provides practical basis for quantum algorithm hardware implementation and reconfigurable quantum accelerator design.

In the future, HOLO will continue along the design philosophy from algorithm to circuit, promoting the hardware implementation of more quantum computing core modules, including quantum variational algorithms (VQE), quantum linear system solvers (QLSA), and FPGA-ization of quantum machine learning models, to build a complete quantum algorithm acceleration ecosystem. It is believed that, through continuous research in this direction, FPGA will become an important bridge between quantum computing and classical computing, providing solid technical support for the industrialization development of quantum technology.

About MicroCloud Hologram Inc.

MicroCloud Hologram Inc. (NASDAQ: HOLO) is committed to the research and development and application of holographic technology. Its holographic technology services include holographic light detection and ranging (LiDAR) solutions based on holographic technology, holographic LiDAR point cloud algorithm architecture design, technical holographic imaging solutions, holographic LiDAR sensor chip design, and holographic vehicle intelligent vision technology, providing services to customers offering holographic advanced driving assistance systems (ADAS). MicroCloud Hologram Inc. provides holographic technology services to global customers. MicroCloud Hologram Inc. also provides holographic digital twin technology services and owns proprietary holographic digital twin technology resource libraries. Its holographic digital twin technology resource library utilizes a combination of holographic digital twin software, digital content, space data-driven data science, holographic digital cloud algorithms, and holographic 3D capture technology to capture shapes and objects in 3D holographic form. MicroCloud Hologram Inc. focuses on developments such as quantum computing and quantum holography, with cash reserves exceeding 3 billion RMB, and plans to invest more than 400 million in USD from the cash reserves to engage in blockchain development, quantum computing technology development, quantum holography technology development, and derivatives and technology development in frontier technology fields such as artificial intelligence AR. MicroCloud Hologram Inc.'s goal is to become a global leading quantum holography and quantum computing technology company.

Safe Harbor Statement

This press release contains forward-looking statements as defined by the Private Securities Litigation Reform Act of 1995. Forward-looking statements include statements concerning plans, objectives, goals, strategies, future events or performance, and underlying assumptions and other statements that are other than statements of historical facts. When the Company uses words such as "may," "will," "intend," "should," "believe," "expect," "anticipate," "project," "estimate," or similar expressions that do not relate solely to historical matters, it is making forward-looking statements. Forward-looking statements are not guarantees of future performance and involve risks and uncertainties that may cause the actual results to differ materially from the Company's expectations discussed in the forward-looking statements. These statements are subject to uncertainties and risks including, but not limited to, the following: the Company's goals and strategies; the Company's future business development; product and service demand and acceptance; changes in technology; economic conditions; reputation and brand; the impact of competition and pricing; government regulations; fluctuations in general economic; financial condition and results of operations; the expected growth of the holographic industry and business conditions in China and the international markets the Company plans to serve and assumptions underlying or related to any of the foregoing and other risks contained in reports filed by the Company with the Securities and Exchange Commission ("SEC"), including the Company's most recently filed Annual Report on Form 10-K and current report on Form 6-K and its subsequent filings. For these reasons, among others, investors are cautioned not to place undue reliance upon any forward-looking statements in this press release. Additional factors are discussed in the Company's filings with the SEC, which are available for review at www.sec.gov. The Company undertakes no obligation to publicly revise these forward-looking statements to reflect events or circumstances that arise after the date hereof.

 

 

 

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SOURCE MicroCloud Hologram Inc.

FAQ

What did MicroCloud Hologram (HOLO) announce on January 16, 2026 about FPGA and quantum simulation?

HOLO announced an FPGA-based algorithm-hardware co-design that maps tensor network computations to parallel FPGA logic to simulate quantum spin models.

How much faster and more efficient is HOLO's FPGA solution compared with CPU?

The company reported a 1.7x speed improvement versus CPU and energy efficiency improved by more than 2x.

How will HOLO fund its planned quantum and frontier technology investments (HOLO)?

HOLO said it holds cash reserves exceeding 3 billion RMB and plans to invest more than 400 million USD from those reserves.

What are the main architectural components of HOLO's FPGA tensor network design?

HOLO described a three-level pipeline: input/scheduling, core MAC-array compute, and output/reduction layers.

Which quantum algorithms does HOLO plan to target next with FPGA acceleration (HOLO)?

The company intends to pursue FPGA implementations for VQE, QLSA, and quantum machine learning models.