Keysight Expands Digital‑Layer Error Performance Validation for High‑Speed 1.6T Interconnects in AI Data Centers

Key Terms

bit error ratio technical

Bit error ratio (BER) measures how often bits—the smallest units of digital information—get flipped or corrupted during transmission, expressed as a fraction or percentage of total bits sent. Think of it as the rate of typos in a long printed manuscript: a higher BER means more errors, which can signal unreliable communications hardware or software, higher repair or compliance costs, and reduced product competitiveness—factors that can affect revenue, margins, and investor confidence.

forward error correction technical

Forward error correction is a way of adding extra information to a digital message so the receiver can spot and fix mistakes without asking for the data to be sent again. For investors, it matters because it improves reliability and speed in networks and devices—reducing delays, lowering bandwidth costs, and enhancing user experience—so products and services that use effective forward error correction can be more competitive and cost-efficient.

pam4 technical

PAM4 is a digital signaling method that sends information by using four distinct voltage or light levels instead of the usual two, letting each transmitted symbol carry two bits of data. Think of it like a radio knob with four clear positions instead of just on/off; it boosts transmission speed without needing extra wires or spectrum but is harder to read reliably, so it matters to investors because it drives demand for higher-performance chips, better cables and optics, and can affect product costs, margins and upgrade cycles in networking and data-center markets.

ieee p802.3dj technical

An IEEE P802.3dj is a standards-development project working on an update to the IEEE 802.3 Ethernet specifications that define how wired network equipment transmits data. For investors, such a standard shapes the technical rules manufacturers and service providers must follow—like a recipe that ensures compatibility and performance—so adoption can influence sales, product cycles, and capital spending across networking and data center companies.

chip-to-module (c2m) technical

Chip-to-module (c2m) is a manufacturing approach where a raw semiconductor chip is mounted and connected directly onto a prepared module or board so it can be used as a ready-made component. For investors, c2m matters because it can cut production steps and costs, speed product launch, and make supply chains more flexible—like bolting an engine onto a chassis instead of building the whole drivetrain from scratch, which can improve margins and shorten time to market.

digital signal processor (dsp) technical

A digital signal processor (DSP) is a specialized microchip that quickly cleans up, compresses or analyzes streams of data such as sound, images or sensor readings using fast math routines. Think of it as a skilled kitchen appliance that chops, seasons and packages raw ingredients so they’re ready for use; for investors, DSPs matter because they enable products and services (from phones and medical devices to radar and streaming) to work efficiently, affecting performance, cost and market competitiveness.

ethernet technical

A wired networking technology that moves data between devices over cables, like a dedicated highway that carries information reliably and quickly across offices, factories, and data centers. Investors care because ethernet underpins the performance and cost of digital services and infrastructure—demand for faster, more reliable wired networks drives spending on hardware, installation and upgrades, which affects manufacturers, service providers and companies that rely on heavy data flow.

Real‑world error performance validation across the full interconnect lifecycle to reduce risk, lower-costs, and ensure reliable components, sub‑assemblies, and complete cable assemblies

SANTA ROSA, Calif.--(BUSINESS WIRE)-- Keysight Technologies, Inc. (NYSE: KEYS) today introduced the Functional Interconnect Test Solutions (FITS) portfolio and FITS-8CH, the suite’s first product. FITS-8CH delivers digital-layer bit error ratio (BER) and forward error correction (FEC) performance validation for high-speed optical and copper interconnects used in network equipment and production network infrastructures.

FITS-8CH delivers real world digital-layer interconnect error performance validation across the development and manufacturing lifecycle.

As interconnect speeds increase and designs grow more complex, manufacturers of chips, optical and copper interconnects, and network equipment face mounting pressure to ensure reliability before products reach mass production and throughout the manufacturing process. Traditional physical-layer test tools play a vital role in validating electrical lanes against industry specifications, establishing a strong compliance baseline. Building on this foundation, system-level validation helps extend insight into the performance of fully integrated interconnects and operational sub-assemblies, including error behavior in realistic environments.

Accurate assessment of real‑world system conditions is only possible when all interconnect electrical or optical lanes undergo high-speed error-performance validation. Without this testing, the risk of production delays or costly failures in the field increases. This includes validating error performance for high‑speed PAM4 electrical lanes operating at 53 Gb/s, 106 Gb/s, and 212 Gb/s, which underpin today’s 400GE, 800GE, and 1.6T Ethernet network architectures.

FITS-8CH addresses this system-level error performance gap by providing multiple-lane error performance validation at the digital layer, supporting PAM4 error performance assessment across all relevant electrical lane speeds and extending beyond physical-layer measurements. This enables reliable validation throughout the design, development, and manufacturing of high-speed interconnects for high-volume deployment in large-scale networks. The chassis also integrates with Keysight’s physical layer test solutions, expanding the number of applications and topologies it supports.

Built for reliability, scale, and manufacturing readiness, FITS‑8CH supports today’s network-testing demands, where even marginal error performance can impact large-scale deployments. Key benefits include:

• Multiple-lane BER and FEC Validation: Enables simultaneous, bi‑directional real-time testing on all eight transmit and eight receive channels, supporting PAM4 signaling speeds from 53 Gb/s to 212.5 Gb/s. Validating system‑level error performance using BER and FEC enables testing of complete optical and copper interconnect assemblies rather than isolated measurements at critical stages, including R&D, product development, in‑process manufacturing, end‑of‑line testing, and system‑level qualification. Using this approach, manufacturers can confidently release verified pre‑production designs to mass production and benchmark reliability under real‑world operating conditions.

• Flexible Channel Architecture: Two complementary channel groups — high‑drive outputs and chip‑to‑module (C2M) interfaces — support a broader range of electrical fixtures and interconnect topologies. This architecture gives teams greater flexibility to support more configurations of electrical fixtures, Ethernet interconnects, active cables, and silicon topologies without redesigning test setups or compromising signal fidelity.

• High‑Quality Signal Generation: IEEE P802.3dj‑compliant signal generation and excellent signal integrity performance even under difficult conditions provide clean, well‑controlled transmit signals required for accurate BER and FEC measurements at all supported channel speeds. By delivering signals that meet defined requirements, teams can evaluate error performance based on the true behavior of the device or interconnect under test, rather than limitations introduced by the test environment. This is especially important in high‑speed, multiple-lane designs, where small signal variations can lead to borderline or misleading results.

• Automated Lane Tuning: Optimizes PAM4 signal output performance with lane‑by‑lane tuning that automatically adjusts transmit tap settings and opens the electrical eye of the PAM4 signal for each lane. This improves measurement consistency and repeatability, reducing the risk of passing assemblies with marginal or borderline error performance.

• Early Detection of Manufacturing and Configuration Issues: Identifies problems such as mechanical misalignment, thermal failures, and non-optimized or incorrect digital signal processor (DSP) tap settings during in‑process or end‑of‑line testing—reducing the costly impact and likelihood of defective products reaching customers.

Kenji Liao, High‑Speed Interconnect PM Director, UDE Corporation, said: “With FITS‑8CH, Keysight provides the digital‑layer error performance analysis we need to verify 1.6T AEC BER‑per‑lane requirements under realistic operating conditions. The ability to characterize lane‑level error behavior across complete interconnect assemblies helps us identify margin issues earlier and maintain consistency as we transition designs into volume production. Integrating this solution into our development and manufacturing workflow strengthens our confidence that UDE’s high‑speed interconnects will meet the stringent performance targets our customers expect. The partnership between UDE and Keysight allows us to use this new solution to support error performance validation across development and manufacturing.”

Ram Periakaruppan, Vice President and General Manager, Network Test & Security Solutions, Keysight, said: “As validation requirements move up the stack from the physical layer, our customers increasingly need solutions that scale across development, manufacturing, and deployment. FITS‑8CH represents Keysight’s expansion into digital‑layer interconnect validation, combining years of deep measurement expertise with the global reach, field support, and portfolio continuity customers rely on for production environments including AI data centers. This is the first offering in our FITS portfolio, a new series of solutions designed to support error performance validation across the entire product lifecycle.”

Keysight will showcase FITS and other network validation solutions in South Hall, booth #1300 from March 17-19, 2026, at the OFC Conference at the Los Angeles Convention Center, Los Angeles, Calif.

Resources

• Product Page: FITS-8CH
• Data Sheet: FITS-8CH Data Sheet

About Keysight Technologies

At Keysight (NYSE: KEYS), we inspire and empower innovators to bring world-changing technologies to life. As an S&P 500 company, we’re delivering market-leading design, emulation, and test solutions to help engineers develop and deploy faster, with less risk, throughout the entire product lifecycle. We’re a global innovation partner enabling customers in communications, industrial automation, aerospace and defense, automotive, semiconductor, and general electronics markets to accelerate innovation to connect and secure the world. Learn more at Keysight Newsroom and www.keysight.com.

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Source: Keysight Technologies, Inc.