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SEALSQ Presented at Tech&Fest How the Quantum Shield QS7001 Can be Integrated as a Hardware Root of Trust to Meet Cryptographic Transition New Legal Requirements Like CNSA 2.0

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SEALSQ (NASDAQ: LAES) presented the QS7001, a quantum-resistant secure microcontroller designed as a hardware root of trust to help devices meet emerging post-quantum mandates like CNSA 2.0.

The QS7001 embeds lattice-based ML-DSA-87 (Dilithium 5), ML-KEM (Kyber), SHA-3, AES-256, TRNG, ROM PQC acceleration and tamper protections for embedded, automotive, and robotics uses.

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News Market Reaction

-1.48%
1 alert
-1.48% News Effect

On the day this news was published, LAES declined 1.48%, reflecting a mild negative market reaction.

Data tracked by StockTitan Argus on the day of publication.

Key Figures

Processor core width: 32-bit Performance improvement: 10x Embedded FLASH: 512 KB
3 metrics
Processor core width 32-bit RISC-V core at heart of QS7001 secure microcontroller
Performance improvement 10x Hardware lattice accelerator vs software-only PQC on conventional MCUs
Embedded FLASH 512 KB On-chip FLASH for firmware image and secure storage

Market Reality Check

Price: $3.85 Vol: Volume 6,546,111 is below...
low vol
$3.85 Last Close
Volume Volume 6,546,111 is below 20-day average 10,454,149 (relative volume 0.63x). low
Technical Price 4.05 is trading above 200-day MA at 3.99 and sits 53.5% below the 52-week high and 103.52% above the 52-week low.

Peers on Argus

LAES gained 2.53% while key semiconductor peers were mixed: NVEC slightly up and...
1 Up

LAES gained 2.53% while key semiconductor peers were mixed: NVEC slightly up and AIP, POET, CEVA, SKYT down. Momentum scanners only flagged POET on the upside, reinforcing a stock-specific move rather than a broad sector rotation.

Historical Context

5 past events · Latest: Feb 06 (Positive)
Pattern 5 events
Date Event Sentiment Move Catalyst
Feb 06 AI threat commentary Positive +13.6% Framed AI advances as reinforcing need for quantum-secure infrastructure.
Feb 04 Conference presentation Positive -4.5% CEO presented sovereign root-to-quantum platform at Tech&Fest.
Jan 29 Expansion and investment Positive -5.9% Expanded French footprint, staff growth targets, and large planned investments.
Jan 28 Event showcase Positive -3.6% Announced Tech&Fest 2026 participation to showcase secure semiconductors.
Jan 27 Platform launch Positive +6.7% Introduced Quantum Highway platform and global Quantum Corridor expansion.
Pattern Detected

Recent news has been mostly positive in tone, but price reactions have been mixed, with several strategic or expansion updates followed by short-term pullbacks alongside occasional strong rallies.

Recent Company History

Over the last few weeks, SEALSQ has issued a series of announcements tied to its quantum-secure strategy. On Jan 27, it unveiled the Quantum Highway platform, followed by Tech&Fest showcase and sovereign security presentations on Jan 28 and Feb 4. A French expansion update on Jan 29 highlighted growing staff and investment. The Feb 6 AI-related note reinforced the quantum-threat narrative. Today’s QS7001-focused news continues this theme of emphasizing post-quantum hardware capabilities and standards alignment.

Market Pulse Summary

This announcement highlights SEALSQ’s QS7001 quantum-resistant secure microcontroller, emphasizing h...
Analysis

This announcement highlights SEALSQ’s QS7001 quantum-resistant secure microcontroller, emphasizing hardware-implemented lattice-based cryptography, CNSA 2.0-aligned ML-DSA-87 and ML-KEM, and tamper-resistant design for robotics, automotive, and critical infrastructure. It extends a recent stream of quantum-security and Tech&Fest-related news. Investors may watch for concrete deployment wins, certification milestones such as Common Criteria EAL5+ or FIPS, and how these technical advances translate into revenue and adoption over time.

Key Terms

hardware root of trust, post-quantum cryptography, lattice-based post-quantum primitive, number theoretic transform (NTT), +4 more
8 terms
hardware root of trust technical
"Can be Integrated as a Hardware Root of Trust to Meet Cryptographic..."
A hardware root of trust is a small, protected set of physical components and code built into a device that creates its secure identity and checks that the device only runs approved software when it powers up. Investors should care because it acts like a tamper‑proof lock that reduces the risk of hacking, data theft and product recalls, supports regulatory compliance and customer trust, and therefore can protect revenue, limit liability and improve market acceptance.
post-quantum cryptography technical
"IoT edge nodes, and other intelligent devices to comply with emerging post-quantum mandates..."
Post-quantum cryptography is a set of new methods for scrambling data so it stays secure even if powerful quantum computers exist; think of replacing today’s locks with designs that a future high‑speed lockpicker cannot open. For investors, it matters because companies must upgrade systems, meet regulations, and protect customer and trade data—creating costs, competitive advantages, or legal and reputational risks depending on how quickly and effectively they adopt these new security standards.
lattice-based post-quantum primitive technical
"the QS7001 implements SHA 3 lattice-based post-quantum primitive directly in silicon..."
A lattice-based post-quantum primitive is a basic cryptographic building block — such as an encryption method, digital signature, or key-exchange technique — that relies on hard mathematical puzzles from lattice structures and is designed to resist attacks by quantum computers. For investors, it matters because these primitives are the foundation for future-proofing digital security: they protect sensitive data, maintain trust in online services, and can affect regulatory compliance, product costs, and the competitiveness of companies handling digital assets.
number theoretic transform (NTT) technical
"a dedicated lattice-math accelerator optimized for: Number Theoretic Transform (NTT) operations..."
A number theoretic transform (NTT) is a mathematical technique that rewrites integer-based data into a different form so certain large numerical operations become much faster, similar to how converting a puzzle to a simpler picture makes it quicker to solve. Investors should care because NTTs are a core tool in modern cryptography and blockchain systems that speed up secure computations, improve transaction throughput, and reduce computing costs, affecting product performance and capital requirements.
true random number generator (TRNG) technical
"AES-256 symmetric encryptionTrue Random Number Generator (TRNG) Hardware & ROM based PQC..."
A true random number generator (TRNG) is a device or system that produces unpredictable numbers by measuring physical processes—like electronic noise or radioactive decay—rather than using a repeating computer formula. Investors care because those genuinely random values are critical for secure encryption, fair gambling, and certain blockchain and cryptographic applications; stronger randomness reduces the risk of hacks or biased outcomes, similar to how a genuine coin flip is harder to predict than a rigged one.
trusted execution environments technical
"secure SRAM partitions, supporting Secure key storageFirmware image storageEncrypted bootloadersTrusted execution environments..."
A trusted execution environment (TEE) is a protected, isolated area inside a computer chip that runs code and stores data separately from the main system so sensitive operations remain secure even if the rest of the device is compromised—think of a locked safe inside a factory floor. Investors care because TEEs reduce the risk of data breaches, enable secure cloud and financial services, help meet regulations, and can be a competitive advantage or a cost factor for companies handling sensitive information.
common criteria eal5+ regulatory
"The QS7001 is engineered for Common Criteria EAL5+ and FIPS certification pathways..."
Common Criteria EAL5+ is a high assurance security certification for hardware or software that means the product has been rigorously tested and reviewed against formal standards, with extra checks beyond the baseline EAL5 level. For investors, it signals lower technical and regulatory risk and can make a product eligible for sensitive government or enterprise contracts—similar to a building passing an advanced safety inspection that unlocks premium tenants.
fips regulatory
"engineered for Common Criteria EAL5+ and FIPS certification pathways and integrates..."
FIPS are standardized numeric codes created by the U.S. government to uniquely identify geographic areas (like states and counties) and certain technical standards. For investors, FIPS codes make it easy to match and analyze location-based data—such as sales, property holdings, regulatory filings or disaster exposure—across different datasets, acting like a postal code for data that helps ensure accuracy and consistency in research and risk assessments.

AI-generated analysis. Not financial advice.

Geneva, Switzerland, Feb. 11, 2026 (GLOBE NEWSWIRE) --

SEALSQ Presented at Tech&Fest How the Quantum Shield QS7001 Can be Integrated as a Hardware Root of Trust to Meet Cryptographic Transition New Legal Requirements Like CNSA 2.0

The quantum resistant chip can be embedded inside robots, autonomous systems, automotive ECUs, industrial controllers, IoT edge nodes, and other intelligent devices to comply with emerging post-quantum mandates and regulation, like CNSA 2.0 or CRA.

SEALSQ Corp (NASDAQ: LAES) ("SEALSQ" or "Company"), a company that focuses on developing and selling Semiconductors, PKI, and Post-Quantum technology hardware and software products, has been showcasing last week its quantum resistant chip, at Tech&Fest, a prominent deep-tech fair at the heart of the European and French research and technology ecosystem in Grenoble.

The QS7001 is a quantum-resistant secure microcontroller (SoC) built around a 32-bit RISC-V core tightly coupled with a dedicated cryptographic acceleration subsystem. Unlike software-based PQC implementations running on general-purpose MCUs, the QS7001 implements SHA 3 lattice-based post-quantum primitive directly in silicon, significantly reducing cycle count, memory footprint, and power consumption while mitigating timing and side-channel leakage risks.

At the core of its CNSA 2.0 compliance is native hardware support for:

  • ML-DSA-87 (Dilithium 5) for firmware and software signing, as required under CNSA 2.0 for high-security environments
  • ML-KEM (Kyber) for quantum-resistant key establishment
  • SHA-3 hardware hashing engines
  • AES-256 symmetric encryption
  • True Random Number Generator (TRNG)

Hardware & ROM based PQC Acceleration
Beyond SHA 3 hardware acceleration, The QS7001 integrates at ROM level a dedicated lattice-math accelerator optimized for:

  • Number Theoretic Transform (NTT) operations
  • Polynomial multiplication over module lattices
  • Rejection sampling and modular reduction
  • Constant-time arithmetic to mitigate timing attacks

By implementing these computationally intensive lattice operations in hardware, the device achieves up to 10x performance improvement versus software-only PQC stacks running on conventional microcontrollers.

Most importantly, Hardware acceleration also reduces RAM usage, enabling full ML-DSA-87 execution within embedded constraints typical of robotics controllers and automotive ECUs.

The chip includes 512 KB embedded FLASH and secure SRAM partitions, supporting

  • Secure key storage
  • Firmware image storage
  • Encrypted bootloaders
  • Trusted execution environments

Secure Boot and Firmware Signing (CNSA 2.0 Alignment)
CNSA 2.0 mandates ML-DSA-87 (Dilithium 5) for firmware and software signing in National Security Systems and high-assurance environments. The QS7001 ML-DSA-87 implementation is protected against side channel attacks and fault injections. The chip also features Anti-rollback firmware protection and cryptographically enforced firmware authenticity and integrity.

Hybrid and Migration Support
CNSA 2.0 defines a transition path from classical public-key cryptography to post-quantum algorithms. The QS7001 supports hybrid cryptographic modes, enabling:

  • Parallel support for ECC/RSA and ML-DSA
  • Hybrid key establishment combining ECDH and ML-KEM
  • Configurable cryptographic policies for phased migration

This ensures backward compatibility with existing infrastructure while enabling forward compliance with NSA timelines.

Tamper Resistance and Physical Security
The QS7001 is engineered for Common Criteria EAL5+ and FIPS certification pathways and integrates:

  • Active tamper detection sensors
  • Voltage, frequency, and glitch monitoring
  • Secure key zeroization on tamper events
  • Side-channel hardened cryptographic engines
  • Memory protection units (MPU)

These protections are essential for robotics, defense systems, autonomous vehicles, and critical infrastructure where physical exposure cannot be ruled out.

Application Integration in Intelligent Systems
Within robotics and intelligent devices, the QS7001 functions as:

  • A secure element for identity provisioning
  • A hardware trust anchor for AI model integrity
  • A secure communication co-processor
  • A TPM-like security controller in embedded architectures

It ensures that:

  • Robot firmware updates are quantum-safe
  • AI models deployed at the edge cannot be altered
  • Device-to-device authentication is resistant to quantum adversaries
  • Telemetry and control channels are encrypted using CNSA 2.0-aligned primitives

CNSA 2.0 is critical because it mandates the transition from classical cryptography (RSA and ECC) to quantum-resistant algorithms to protect national security systems against future quantum-computing threats. It addresses the “harvest now, decrypt later” risk, where adversaries can capture encrypted data today and decrypt it once quantum computers become powerful enough.

A key requirement is the use of ML-DSA-87 (Dilithium 5) for firmware and software signing, ensuring that secure boot and system integrity remain protected in a post-quantum world. It also mandates ML-KEM (Kyber) for quantum-safe key exchange, safeguarding encrypted communications and device authentication.

CNSA 2.0 is not just a cryptographic update — it is a strategic shift that forces governments, defense contractors, and technology providers to redesign hardware, firmware, and infrastructure with long-term quantum resilience built in.

The moment is critical to accelerate the migration to Post-Quantum Cryptography (PQC). As quantum technologies rapidly advance, governments are moving decisively to secure strategic leadership.

About SEALSQ:
SEALSQ is a leading innovator in Post-Quantum Technology hardware and software solutions. Our technology seamlessly integrates Semiconductors, PKI (Public Key Infrastructure), and Provisioning Services, with a strategic emphasis on developing state-of-the-art Quantum Resistant Cryptography and Semiconductors designed to address the urgent security challenges posed by quantum computing. As quantum computers advance, traditional cryptographic methods like RSA and Elliptic Curve Cryptography (ECC) are increasingly vulnerable.

SEALSQ is pioneering the development of Post-Quantum Semiconductors that provide robust, future-proof protection for sensitive data across a wide range of applications, including Multi-Factor Authentication tokens, Smart Energy, Medical and Healthcare Systems, Defense, IT Network Infrastructure, Automotive, and Industrial Automation and Control Systems. By embedding Post-Quantum Cryptography into our semiconductor solutions, SEALSQ ensures that organizations stay protected against quantum threats. Our products are engineered to safeguard critical systems, enhancing resilience and security across diverse industries.

For more information on our Post-Quantum Semiconductors and security solutions, please visit www.sealsq.com.

Forward-Looking Statements
This communication expressly or implicitly contains certain forward-looking statements concerning SEALSQ Corp and its businesses. Forward-looking statements include statements regarding our business strategy, financial performance, results of operations, market data, events or developments that we expect or anticipate will occur in the future, as well as any other statements which are not historical facts. Although we believe that the expectations reflected in such forward-looking statements are reasonable, no assurance can be given that such expectations will prove to have been correct. These statements involve known and unknown risks and are based upon a number of assumptions and estimates which are inherently subject to significant uncertainties and contingencies, many of which are beyond our control. Actual results may differ materially from those expressed or implied by such forward-looking statements. Important factors that, in our view, could cause actual results to differ materially from those discussed in the forward-looking statements include SEALSQ's ability to continue beneficial transactions with material parties, including a limited number of significant customers; market demand and semiconductor industry conditions; and the risks discussed in SEALSQ's filings with the SEC. Risks and uncertainties are further described in reports filed by SEALSQ with the SEC.

SEALSQ Corp is providing this communication as of this date and does not undertake to update any forward-looking statements contained herein as a result of new information, future events or otherwise.

SEALSQ Corp.
Carlos Moreira
Chairman & CEO
Tel: +41 22 594 3000
info@sealsq.com
SEALSQ Investor Relations (US)
The Equity Group Inc.
Lena Cati
Tel: +1 212 836-9611
lcati@theequitygroup.com



FAQ

What is the QS7001 announced by SEALSQ (LAES) on February 11, 2026?

The QS7001 is a quantum-resistant secure microcontroller designed as a hardware root of trust. According to the company, it implements lattice-based ML-DSA-87 and ML-KEM with SHA-3, AES-256, TRNG and ROM-level PQC acceleration for embedded systems.

How does the QS7001 help LAES customers comply with CNSA 2.0 requirements?

QS7001 supports CNSA 2.0 primitives required for high-assurance systems, enabling post-quantum firmware signing. According to the company, it provides ML-DSA-87 firmware signing, ML-KEM key exchange, secure boot and anti-rollback protections.

What performance advantage does SEALSQ claim for the QS7001 versus software-only PQC?

The device achieves up to 10x performance improvement over software-only PQC stacks on conventional microcontrollers. According to the company, hardware lattice accelerators reduce cycle count, RAM usage and power while lowering side-channel risks.

Which embedded applications did SEALSQ target for the QS7001 (LAES)?

SEALSQ targets robotics, autonomous systems, automotive ECUs, industrial controllers and IoT edge nodes. According to the company, QS7001 acts as a secure element, TPM-like controller and hardware trust anchor for AI model and firmware integrity.

What physical and certification protections does the QS7001 include for high-security deployments?

QS7001 integrates tamper detection, glitch monitoring, secure key zeroization and side-channel hardening for physical security. According to the company, it is engineered for Common Criteria EAL5+ and FIPS certification pathways and secure memory partitions.
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