Nano Labs Launches FPU3.0 ASIC Design Architecture with 3D DRAM Stacking for AI and Blockchain Innovation

Rhea-AI Summary

Nano Labs (Nasdaq: NA) has unveiled FPU3.0, a new ASIC architecture featuring advanced 3D DRAM stacking technology. The architecture achieves a fivefold improvement in power efficiency compared to its predecessor, FPU2.0. The design is optimized for AI inference and blockchain applications.

The FPU architecture consists of four core modules: Smart NOC (Network-on-Chip), high-bandwidth memory controller, chip-to-chip interconnect IOs, and FPU core. The FPU3.0 specifically incorporates stacked 3D memory with 24TB/s theoretical bandwidth and an upgraded Smart-NOC on-chip network, supporting various compute cores and traffic types.

Positive

• Achieved 5x power efficiency improvement over previous generation
• Implemented advanced 3D DRAM stacking technology
• Achieved 24TB/s theoretical bandwidth capability
• Modular design enables rapid product iteration

Negative

• None.

HONG KONG, Dec. 26, 2024 /PRNewswire/ -- Nano Labs Ltd (Nasdaq: NA) ("we," the "Company," or "Nano Labs"), a leading fabless integrated circuit design company and product solution provider in China, today announced the launch of FPU3.0, an ASIC architecture designed to enhance artificial intelligence (AI) inference and blockchain performance. Featuring advanced 3D DRAM stacking technology, FPU3.0 delivers a fivefold boost in power efficiency over the previous FPU2.0 architecture, setting a new standard for energy-efficient, high-performance ASICs. This latest advancement highlights the Company's robust research and development capabilities in adopting cutting-edge technologies and its commitment to driving innovation and widespread adoption in the AI and cryptocurrency industry.

The FPU series represents Nano Labs' proprietary set of ASIC chip design architectures, purpose-built for high-bandwidth High Throughput Computing (HTC) applications. Such ASIC chips are optimized for specific functions or applications, typically delivering lower power consumption and higher computational efficiency than general-purpose CPUs and GP-GPUs. These ASICs are increasingly utilized in AI inference, edge AI computing, data transmission processing under 5G networks, network acceleration, and more.

The Nano FPU architecture comprises four fundamental modules and IPs: the Smart NOC (Network-on-Chip), the high-bandwidth memory controller, the chip-to-chip interconnect IOs, and the FPU core. This modular provides remarkable flexibility, enabling rapid product iteration by updating the FPU core IP while reusing or upgrading other IPs and modules as needed - often sufficient to introduce new features.

Notably, the FPU3.0 architecture incorporates stacked 3D memory with a theoretical bandwidth of 24TB/s and an upgraded Smart-NOC on-chip network. This network supports a mix of large and small compute cores, full-crossbar, and feed-through traffic types on the bus. The FPU3.0 architecture holds the potentials to excel in various fields, delivering superior performance, lower power consumption, and faster product iteration cycles.

About Nano Labs Ltd

Nano Labs Ltd is a leading fabless integrated circuit ("IC") design company and product solution provider in China. Nano Labs is committed to the development of high throughput computing ("HTC") chips, high performance computing ("HPC") chips, distributed computing and storage solutions, smart network interface cards ("NICs") vision computing chips and distributed rendering. Nano Labs has built a comprehensive flow processing unit ("FPU") architecture which offers solution that integrates the features of both HTC and HPC. Nano Lab's Cuckoo series are one of the first near-memory HTC chips available in the market*. For more information, please visit the Company's website at: ir.nano.cn.

* According to an industry report prepared by Frost & Sullivan.

Forward-Looking Statements

This press release contains forward-looking statements within the meaning of Section 21E of the Securities Exchange Act of 1934, as amended, and as defined in the U.S. Private Securities Litigation Reform Act of 1995. These forward-looking statements include, without limitation, the Company's plan to appeal the Staff's determination, which can be identified by terminology such as "may," "will," "expect," "anticipate," "aim," "estimate," "intend," "plan," "believe," "potential," "continue," "is/are likely to" or other similar expressions. Such statements are based upon management's current expectations and current market and operating conditions, and relate to events that involve known or unknown risks, uncertainties and other factors, all of which are difficult to predict and many of which are beyond the Company's control, which may cause the Company's actual results, performance or achievements to differ materially from those in the forward-looking statements. Further information regarding these and other risks, uncertainties or factors is included in the Company's filings with the Securities and Exchange Commission. The Company does not undertake any obligation to update any forward-looking statement as a result of new information, future events or otherwise, except as required under law.

For investor inquiries, please contact:

Nano Labs Ltd
ir@nano.cn 

Ascent Investor Relations LLC
Tina Xiao
Phone: +1-646-932-7242
Email: investors@ascent-ir.com

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SOURCE Nano Labs Ltd

FAQ

What is the power efficiency improvement of Nano Labs' (NA) FPU3.0 compared to FPU2.0?

Nano Labs' FPU3.0 achieves a fivefold (5x) improvement in power efficiency compared to the previous FPU2.0 architecture.

What is the theoretical bandwidth of Nano Labs' (NA) FPU3.0 3D memory?

The FPU3.0's stacked 3D memory has a theoretical bandwidth of 24TB/s.

What are the four fundamental modules of Nano Labs' (NA) FPU architecture?

The FPU architecture comprises Smart NOC (Network-on-Chip), high-bandwidth memory controller, chip-to-chip interconnect IOs, and FPU core.

What applications is Nano Labs' (NA) FPU3.0 ASIC designed for?

FPU3.0 is designed for AI inference, blockchain applications, edge AI computing, data transmission processing under 5G networks, and network acceleration.