Welcome to our dedicated page for Quicklogic news (Ticker: QUIK), a resource for investors and traders seeking the latest updates and insights on Quicklogic stock.
QuickLogic Corporation reports developments in fabless semiconductor products built around embedded FPGA technology, ruggedized programmable logic and specialized FPGA devices. News commonly covers eFPGA Hard IP, Strategic Radiation Hardened and Antifuse FPGAs, chiplet-related offerings, endpoint AI solutions and low-power platforms such as the EOS S3 SoC for always-on sensing applications.
Company updates also include customer contracts for advanced process technologies, technical demonstrations of RadPro FPGA development tools, sales-channel appointments, conference presentations, quarterly financial results and capital resources such as revolving credit facilities. The recurring business themes center on programmable logic for aerospace and defense, industrial, computing, consumer and embedded edge applications.
QuickLogic (NASDAQ: QUIK) will exhibit and present at Chiplet Summit 2026 in Santa Clara, Feb 17–19. The company will staff Booth #416 to demo eFPGA IP and eFPGA-based chiplets and will deliver a technical session on Feb 19 titled "Enabling Flexible Heterogeneous Integration with an eFPGA Chiplet on Intel® 18A".
The presentation by Trey Peterson, Applications Engineer, is scheduled for Session E-202 on Feb 19 from 3:00 p.m. to 4:20 p.m.
QuickLogic (NASDAQ: QUIK) scheduled its fiscal 2025 fourth quarter and full year results call for Tuesday, March 3, 2026 at 5:30 p.m. ET / 2:30 p.m. PT. Dial-in and replay details were provided and a webcast will be posted on the company's investor relations events page and archived for 12 months.
QuickLogic (NASDAQ: QUIK) announced it has received orders for its Strategic Radiation Hardened FPGA Development Kit (SRH FPGA Dev Kit). The kits include SRH FPGA test chips that QuickLogic funded and had fabricated on GlobalFoundries' 12 nm process. Delivery of the SRH FPGA Dev Kit is scheduled for late Q1 2026. The company said the test chip was designed to meet requirements of certain large Defense Industrial Base customers with programs in development and that the kits support both discrete SRH FPGA and embedded SRH FPGA-in-ASIC design evaluations.
QuickLogic (NASDAQ: QUIK) announced an expanded scope for its Prime U.S. government Strategic Radiation Hardened (SRH) FPGA contract, increasing the total ceiling to approximately $88 million over multiple years.
The contract work is sponsored under DoD's Trusted and Assured Microelectronics (T&AM) Program with Naval Surface Warfare Center Crane as technical lead. QuickLogic said it has completed the design and taped out a test FPGA chip to be fabricated by GlobalFoundries on its 12LP process.
QuickLogic (NASDAQ: QUIK) announced its eFPGA Hard IP was selected by the University of Saskatchewan STARR-Lab to personalize the next-generation StarRISC rad-tolerant RISC-V microcontroller. The design will be taped out on Globalfoundries 12nm FinFET and is partially supported by GF's University Research Program.
Integration of eFPGA enables on-chip prototyping of custom logic blocks, accelerators, and mission-specific algorithms for space and high-reliability environments. QuickLogic highlighted delivery timelines of 4–6 months to provide fab-specific Hard IP and customer variants in weeks, supported by its Australis IP Generator and two toolchains: Aurora (open-source) and Aurora Pro (Synopsys Synplify integration).
QuickLogic (NASDAQ: QUIK) announced that Idaho Scientific selected QuickLogic's eFPGA Hard IP to enable crypto‑agile, hardware‑based cryptographic solutions and root of trust capabilities for mobile, IoT, infrastructure, and defense systems.
The eFPGA IP is presented as a way to iterate cryptographic techniques without multiple tapeouts, reducing design risk and cost and accelerating development. QuickLogic says it can deliver fab‑specific Hard IP on a new process node in 4–6 months, with customer variants available in weeks via its Australis IP Generator. The IP is supported by two tool suites: Aurora (open source) and Aurora Pro (integrates Synopsys Synplify).
QuickLogic (NASDAQ: QUIK) announced its eFPGA Hard IP was selected by Chipus for a high-performance data center production ASIC to be fabricated on a 12 nm process.
The selection highlights eFPGA as a central design requirement and emphasizes QuickLogic's silicon-proven IP, its ability to reduce ASIC risk and shorten schedules, and delivery timelines of 4–6 months for fab-specific Hard IP and customer variants in weeks via the Australis IP Generator. Tool support includes open-source Aurora and Aurora Pro with Synopsys Synplify integration.
QuickLogic (NASDAQ: QUIK) reported fiscal Q3 2025 results for the quarter ended September 28, 2025, showing a sharp revenue decline and widened losses.
Total revenue was $2.0M, down 51.8% year‑over‑year and down 45.0% sequentially. New product revenue fell to about $1.0M (-72.6% YoY). GAAP gross margin was −23.3% and non‑GAAP gross margin was −11.9%. GAAP operating expenses were $3.5M; non‑GAAP operating expenses were $2.9M. GAAP net loss was $4.0M (−$0.24/share); non‑GAAP net loss was $3.2M (−$0.19/share).
Highlights include a $1M eFPGA Hard IP contract, renewed USG Strategic Rad Hard FPGA activity expected to help Q4, expanded defense engagements, and a new board appointment.
QuickLogic (NASDAQ: QUIK) will exhibit at Space Tech Expo Europe 2025 in Bremen, Germany, Nov 18–20, 2025 at Hall 6, Stand R19. The company promotes its silicon-proven, export-compliant (EAR99) embedded FPGA (eFPGA) Hard IP and radiation‑tolerant FPGA solutions for aerospace and defense.
QuickLogic highlights its Australis™ IP Generator, which can deliver customer‑specific eFPGA Hard IP within weeks for established nodes and in 4–6 months for new nodes, aiming to shorten design cycles, lower redesign costs, and support long‑term mission adaptability.
QuickLogic (NASDAQ: QUIK) will exhibit at Embedded World North America 2025 in Anaheim, Nov 4–6, 2025 at Booth #5027. The company will demo its Australis eFPGA IP Generator, a fully automated tool that produces custom eFPGA Hard IP optimized for power, performance, and area and compatible with standard ASIC flows and open-source FPGA user tools. QuickLogic will also present its eFPGA chiplet technology—scalable, UCIe-connected chiplets designed to add reconfigurable logic and secure, customizable acceleration to heterogeneous SoCs and embedded systems.
Attendees can learn about integration benefits, PPA optimization, and how QuickLogic’s solutions aim to extend product longevity and design flexibility for embedded applications.