ASE Launches Automated 310mm Panel-Level Packaging to Accelerate AI Innovation

Key Terms

panel-level packaging technical

Panel-level packaging is a manufacturing approach that packages many chips or electronic components while they are still on a large flat sheet or panel, rather than handling each tiny piece individually. Like wrapping an entire sheet of cookies at once instead of one cookie at a time, it can lower per-unit costs, speed up production, and improve consistency across devices; those effects influence unit margins, production capacity and the pace at which new products reach the market.

wafer-level packaging technical

Wafer-level packaging is a chip-making method where the protective casing and connections are added while the entire silicon wafer is still intact, before it’s cut into individual chips. Think of it like packaging cookies while they’re still on the baking sheet so you save steps and space; for investors, this can mean smaller, faster, lower-cost components, higher production efficiency and potentially better profit margins or competitive advantage for companies that adopt it.

heterogeneous integration technical

Heterogeneous integration is the practice of combining different types of electronic components — such as processors, memory, sensors and specialized chips — into a single package or tightly linked module, rather than building everything on one uniform chip. Like putting varied ingredients into one compact lunchbox to save space and improve function, it matters to investors because it can boost product performance, lower power use, shorten development time and create competitive or cost advantages that affect revenue and margins.

system-in-package technical

A system-in-package (SiP) is a single physical package that contains multiple electronic components — such as processors, memory, sensors and power management — designed to work together as one unit. For investors, SiPs matter because they can shrink product size, speed time-to-market and lower assembly costs while concentrating supplier and manufacturing risks; think of it like buying a compact, ready-made toolkit instead of sourcing and assembling each tool separately.

chiplets technical

Small, individual semiconductor components that are manufactured separately and then combined into a single package to perform the function of a larger chip. Like using Lego bricks instead of carving one big block, chiplets let designers mix and match proven parts to reduce cost, shorten development time, improve manufacturing yields and enable upgrades; investors watch them because they can lower production risk, boost product competitiveness and affect profit margins across the semiconductor supply chain.

high-bandwidth memory (HBM) technical

High-bandwidth memory (HBM) is a type of computer memory engineered to move very large amounts of data quickly between memory and processors by stacking memory chips and using wide, short connections for faster, more efficient transfers. It matters to investors because HBM can significantly boost performance and lower power use in data centers, AI systems and high-end chips, affecting demand and profitability for chipmakers and their suppliers — like widening a highway so more traffic moves faster with less congestion.

system-in-package (SiP) technical

A system-in-package (SiP) is a compact module that combines multiple electronic components—such as processors, memory, sensors and power controllers—into a single sealed unit so they work together like a mini computer. For investors, SiPs matter because they can cut product size and manufacturing cost, speed development, and enable new product features, which affects a company’s competitiveness, margins and supply‑chain risks much like packing several stores into one mall affects rent and operations.

Driving performance, scalability, and efficiency for next-generation compute workloads

SUNNYVALE, Calif.--(BUSINESS WIRE)-- Advanced Semiconductor Engineering, Inc. (ASE), a member of ASE Technology Holding Co., Ltd. (NYSE: ASX, TAIEX: 3711) and a leading provider of semiconductor assembly and test services, today announced the development of an industry-first automated 310mm × 310mm panel-level packaging production line, advancing its leadership in next-generation advanced packaging technologies. This milestone expands economies of scale by enabling a seamless transition from wafer-level packaging to panel-level packaging while preserving design rule consistency across FOCoS and FOCoS-Bridge packaging platforms. The new panel line is expected to enter production in the first half of 2027.

The announcement further accentuates ASE’s commitment to enabling the semiconductor industry’s transition into the era of heterogeneous integration, where performance is increasingly defined by high-bandwidth, low-latency interconnects across chiplets, ASICs, and high-bandwidth memory (HBM). As AI accelerators and high-performance computing (HPC) devices grow in complexity, panel-level packaging represents a critical innovation to support the roadmap toward trillion-transistor system-in-package architectures.

ASE’s automated panel-level packaging line supports 310mm × 310mm format and is compatible with advanced packaging platforms including FOCoS and FOCoS-Bridge, delivering line/space capabilities of 2/2µm and 8/8µm, respectively. By transitioning from traditional round wafers to rectangular panels, ASE enables significantly greater usable area—up to 96,100 mm² per panel—allowing for more dies per unit and improved material efficiency.

This shift to panel-level packaging addresses critical industry challenges, including rising interposer sizes and declining wafer-level efficiency. The larger panel format supports higher throughput and reduced cycle time, while enabling integration of increasingly complex multi-die architectures. These benefits are especially impactful for AI data center and HPC applications, where demand for larger package sizes and higher I/O density continues to accelerate.

“ASE is driving a fundamental shift in advanced packaging by introducing an automated panel-level manufacturing platform that significantly improves scalability and efficiency,” said Dr. C. P. Hung, Vice President of Corporate Research and Development at ASE. “This innovation enables higher integration density and supports the evolving requirements of AI and HPC systems, where performance, power efficiency, and manufacturability must be addressed holistically.”

The panel-level platform delivers higher throughput through large-area processing and reduced tool change steps, while offering a flexible foundation for heterogeneous integration and system-in-package (SiP) solutions. It supports a wide range of applications including AI, HPC, networking, high-end gaming, and edge AI, helping customers meet performance targets with greater manufacturing efficiency and faster time-to-market.

“Panel-level packaging represents a pivotal step in enabling the next wave of AI-driven innovation,” said Yin Chang, Executive Vice President at ASE. “As AI training and inference workloads scale, achieving the highest levels of system performance requires not only advanced silicon, but also advances in packaging efficiency and integration. Our panel-level platform enhances throughput, optimizes material utilization, and delivers the scalability needed for increasingly complex computing architectures across a broad range of applications, with hyperscale customers continuing to drive the pace of innovation.”

ASE’s new solution also reinforces its competitive differentiation through faster cycle times, scalable manufacturing, and alignment with long-term industry roadmaps for chiplet-based architectures and large-form-factor integration. As the industry moves beyond the limitations of traditional wafer-based processes, ASE continues to lead in delivering advanced packaging solutions that enable new levels of system performance and efficiency.

ASE will participate in the 76th IEEE Electronic Components and Technology Conference (ECTC) in Orlando, Florida, from May 26 to May 29, 2026. Dr. Tien Wu, ASE’s Chief Executive Officer, will deliver the plenary keynote titled “Advanced Packaging & the Future of System Optimization.” Executive Vice President Yin Chang and Corporate Vice President Dr. C. P. Hung will also participate in special panel sessions, covering “Enabling Next-Generation Advanced Packaging Technology – From Wafer to Panel” and “Co-Design in High-Performance Packaging,” respectively.

Supporting resources

• For more, please visit: https://ase.aseglobal.com/310x310
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About ASE, Inc.

ASE, Inc. is the leading global provider of semiconductor manufacturing services in assembly and test. Alongside a broad portfolio of established assembly and test technologies, ASE is also delivering innovative VIPack™, advanced packaging, and system-in-package solutions to meet growth momentum across a broad range of end markets, including AI, Automotive, 5G, High-Performance Computing, and more. To learn about our advances in SiP, Fanout, MEMS & Sensor, Flip Chip, and 2.5D, 3D & TSV technologies, all ultimately geared towards applications to improve lifestyle and efficiency, please visit: aseglobal.com or follow us on LinkedIn & X: @aseglobal.

View source version on businesswire.com: https://www.businesswire.com/news/home/20260526442808/en/

Media Contacts:
North America & Europe: Patricia MacLeod +1.408.314.9740 patricia.macleod@aseus.com
Asia Pacific: Jennifer Yuen +65 97501975 jennifer.yuen@aseus.com

Source: ASE, Inc.