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Cadence Design Systems develops electronic design automation software, design IP, and system design and analysis products for semiconductor and system engineering. Company updates commonly cover AI-driven chip design, certified design flows for advanced process nodes, digital twins, physics-based simulation, and computational software used from silicon design to electromechanical systems.
Recurring developments include collaborations with semiconductor, cloud and accelerated-computing partners; customer adoption of technologies such as Tensilica Vision DSP IP and Cadence ChipStack AI Super Agent; and financial results across EDA, IP, and system design and analysis. Cadence also reports on expanded simulation capabilities, including structural and multibody dynamics technologies added through the completed Hexagon design and engineering acquisition.
Cadence (CDNS) announced an expanded partnership with TSMC to deliver certified EDA tool flows and silicon-proven IP for AI and high-performance computing designs on TSMC’s most advanced process technologies.
Cadence’s digital, analog and signoff flows are now certified for TSMC A16™, A14 and N2P, and the company has demonstrated an industry-leading UALink solution in TSMC N3P while introducing new silicon-proven IP for N3P and N2P. The collaboration also enables agentic AI and 3D-IC design flows across TSMC’s N3, N2, A16 and A14 nodes, supports TSMC 3DFabric® for wafer-scale systems with hundreds of chiplets, and adds expanded support for TSMC-COUPE™ photonic connectivity, CoWoS® architectures and SoW-X flows.
Cadence (CDNS) introduced a new RTL Generation Agent within its ChipStack AI Super Agent that automates PPA-driven spec-to-RTL creation, analysis and refinement from natural-language prompts.
The agent extends ChipStack from autonomous verification and debug into high-quality RTL generation and optimization, leveraging Cadence’s implementation and signoff engines. In early evaluations, it achieved an average 24% area reduction and 18% power reduction versus pure foundation model code generation while maintaining 100% functional accuracy. Honda R&D is evaluating the technology on advanced automotive SoCs. Expanded ChipStack and InnoStack AI Super Agent capabilities are expected to be available to select early-access customers in Q4 2026.
Cadence (CDNS) is supplying Tensilica DSP IP for Analog Devices' next-generation SHARC automotive audio processors. The collaboration integrates a custom Tensilica-based SHARC-FX core into ADI’s new ADSP-SC84x/2184x platform, intended for premium in-vehicle audio and voice applications. Built on 16nm process technology versus the prior 28nm node, the platform targets higher energy efficiency, operating frequencies, and integration for software-defined vehicles.
The SHARC-FX architecture supports more data types, enhanced VLIW SIMD, expanded instruction set and optimized cache, delivering about 5X performance over the previous SHARC+ core in ADSP-SC59x. It is optimized for on-chip AI/ML and signal-processing workloads, enabling tasks such as music genre identification, source separation and real-time neural-network-based audio at the edge. ADI also offers a supporting toolchain, including Cadence compilers, EZ-KIT evaluation systems and frameworks like DSP Concepts’ Audio Weaver.
Cadence Design Systems (CDNS)/b) announced that president and CEO Dr. Anirudh Devgan will join a fireside chat at the Goldman Sachs Communacopia + Technology Conference in San Francisco on Wednesday, September 9, 2026.The session will be webcast live at 10:50 a.m. PDT and hosted at investor.cadence.com, where a replay will remain available for 180 days.
Cadence (Nasdaq: CDNS) announced that its complete PCIe 6.0 x8 subsystem—combining PHY and controller IP on the TSMC N3 process—achieved first-pass compliance at PCI-SIG’s inaugural PCIe 6.0 specification workshop, successfully operating at 64 GT/s and being added to the PCI-SIG Integrators List.
The subsystem targets AI and high-performance computing data centers, offering ADC/DSP-based equalization, firmware-optimized SerDes, multi-protocol flexibility, and low-power features aligned with recent PCI-SIG ECNs. Cadence noted early ecosystem collaboration and highlighted customer adoption, including Positron AI’s licensing of its SerDes IP for an AI inference accelerator chip.
Cadence (Nasdaq: CDNS) announced that vice president of investor relations Richard Gu will participate in a fireside chat at the Deutsche Bank Technology Conference on Wednesday, August 26, 2026. The session will be webcast live at 12:25 p.m. PDT and accessible via the Cadence investor relations website. The webcast replay will be archived for 180 days, allowing extended access for investors and other interested viewers.
Cadence (Nasdaq: CDNS) reported second quarter 2026 revenue of $1.584 billion, up from $1.275 billion in Q2 2025, with GAAP operating margin of 28.4% and non-GAAP operating margin of 45.5%. GAAP diluted EPS was $1.33 versus $0.59, and non-GAAP diluted EPS was $2.11 versus $1.65.
Quarter-end backlog reached a record $8.1 billion, with $4.2 billion expected to be recognized in the next 12 months. According to Cadence, the company raised its 2026 outlook to 19% revenue growth, targeting non-GAAP operating margin of 44.25%, non-GAAP EPS of $8.10, and operating cash flow of $2 billion at the midpoint. Full-year 2026 revenue is now expected between $6.26–$6.34 billion, with GAAP EPS of $4.76–$4.86 and non-GAAP EPS of $8.05–$8.15.
Business highlights include launching the AuraStack AI Super Agent, strong early traction across the AI Super Agents portfolio, IP revenue growth of over 40% year-over-year, Core EDA revenue growth of 18%, System Design and Analysis revenue growth of 37%, and another record hardware quarter adding 12 new customers.
Cadence (Nasdaq: CDNS) and Rapidus Corporation announced a collaboration to integrate the Cadence InnoStack AI Super Agent into the Rapidus AI-Agentic Design Solution (Raads) for advanced-node SoC design. The companies aim to improve productivity, design quality and time to market, with Rapidus targeting up to a 2X reduction in design turnaround time versus traditional flows.
Rapidus is expanding its Raads lineup with Raads Navigator and Raads Indicator, which are integrated with InnoStack to orchestrate agentic AI across key SoC workflows. The collaboration will be highlighted at CadenceLIVE Japan 2026 in a keynote by Rapidus CEO Atsuyoshi Koike.
Cadence (Nasdaq: CDNS) launched the AuraStack AI Super Agent on Allegro AI Studio, described as the first agentic AI platform for PCB and advanced packaging design, spanning system planning through manufacturing. Accelerated by NVIDIA Blackwell and CUDA‑X, it coordinates domain‑specific AI agents across planning, implementation and multiphysics analysis.
According to Cadence, AuraStack can deliver up to 2X faster time to market, 15X higher productivity and a unified multiphysics foundation for electrical, thermal and mechanical optimization. Cadence highlights collaborations with NVIDIA, TSMC, Socionext, FORVIA HELLA and Schneider Electric. AuraStack AI Super Agent is planned to be available in 2026.
Cadence (Nasdaq: CDNS) will host its second quarter 2026 financial results webcast on Monday, July 27, 2026, starting at 2:00 p.m. Pacific Time.
The event will feature CEO Anirudh Devgan and CFO John Wall, with a replay available at investor.cadence.com until the third quarter 2026 results call.