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Cadence Design Systems develops electronic design automation software, design IP, and system design and analysis products for semiconductor and system engineering. Company updates commonly cover AI-driven chip design, certified design flows for advanced process nodes, digital twins, physics-based simulation, and computational software used from silicon design to electromechanical systems.
Recurring developments include collaborations with semiconductor, cloud and accelerated-computing partners; customer adoption of technologies such as Tensilica Vision DSP IP and Cadence ChipStack AI Super Agent; and financial results across EDA, IP, and system design and analysis. Cadence also reports on expanded simulation capabilities, including structural and multibody dynamics technologies added through the completed Hexagon design and engineering acquisition.
Cadence Design Systems (Nasdaq: CDNS) launched its new Cadence System-Level Verification IP (System VIP) to enhance system-on-chip (SoC) verification. The suite automates testbench assembly, traffic generation, and performance analysis, achieving up to 10X efficiency in chip-level verification. Key components include the System Testbench Generator, System Traffic Libraries, System Performance Analyzer, and System Verification Scoreboard. The solution extends Cadence’s leadership in IP-level verification to chip-level challenges, ensuring better throughput and quality in complex SoC designs.
Cadence Design Systems (Nasdaq: CDNS) announced that TriEye utilized the Cadence® Spectre® X Simulator to expedite the design of a next-generation CMOS-based Short-Wave Infrared (SWIR) image sensor by several months. TriEye achieved a 2X performance increase over prior simulators while ensuring ISO compliance for automotive applications. The Spectre X Simulator, known for its accuracy in handling complex designs, allowed TriEye to optimize their development process, significantly reducing time to market.
Cadence Design Systems (Nasdaq: CDNS) has announced that its Pegasus Verification System has received certification from TSMC for the N16, N12, and N7 process technologies. This certification allows customers to efficiently achieve physical verification with TSMC-certified rule decks. The system facilitates massive job distribution on various hardware, optimizing performance with TSMC’s advanced processes. This collaboration aims to enhance design cycle efficiency and accuracy for applications in AI, automotive, and data centers.
Cadence Design Systems (Nasdaq: CDNS) announced its silicon-proven Cadence IP for GDDR6 on TSMC’s N6 and N7 processes, with plans for N5 implementation. This Design IP enables high-bandwidth memory applications, crucial for AI, 5G, and hyperscale computing. The GDDR6 architecture offers over 2X the data rate of DDR5 and LPDDR5, achieving 16Gbit/s bandwidth per pin and 512Gbit/s per chip. Cadence's collaboration with TSMC and Micron focuses on enhancing performance and power efficiency for next-gen memory-intensive solutions.
Cadence Design Systems (CDNS) will host a live webcast on October 19, 2020 to discuss its third quarter financial results. The event will feature CEO Lip-Bu Tan and CFO John Wall, starting at 2:00 PM PT. An archive of the webcast will be accessible online from 5:00 PM PT on the same day until December 18, 2020. Cadence continues to lead in electronic design, leveraging over 30 years of software expertise to support innovative companies across various sectors. More details can be found at cadence.com/cadence/investor_relations.