Cadence Collaborates With TSMC to Deliver Certified Tool Solutions and Industry-Leading, Silicon-Proven UALink IP on TSMC Advanced Processes

Cadence expands its certified tools and silicon-proven IP on TSMC’s latest process nodes, targeting complex AI, HPC and wafer-scale 3D-IC designs.

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Expanded partnership spans TSMC A14 certification, silicon-proven IP on TSMC N3P/N2P, wafer-scale 3D-IC for hundreds of chiplets, and agentic AI flows

SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence (Nasdaq: CDNS) today announced an expanded partnership with TSMC to deliver advanced capabilities for AI and HPC designers. Cadence has achieved tool certification for TSMC’s advanced A14 process, demonstrated an industry-leading UALink solution in TSMC N3P, and introduced new silicon-proven IP for N3P and N2P technologies. Through this partnership, the companies are enabling agentic AI chip and 3D-IC design flows across TSMC's N3, N2, A16™ and A14 process technologies, including TSMC 3DFabric® support for wafer-scale systems with hundreds of chiplets.

“Cadence's partnership with TSMC continues to deliver breakthrough innovations that enable leading‑edge customers to accelerate their most advanced semiconductor designs," said Chin‑Chi Teng, senior vice president and general manager of the Digital and Signoff Group at Cadence. "With AI‑driven design flows, silicon‑proven IP and 3D-IC solutions, we're helping customers achieve faster time to market and improved PPA on TSMC's leading‑edge process technologies.”

“TSMC, together with our Open Innovation Platform® (OIP) partners like Cadence, is addressing the key demands of semiconductor development to achieve higher performance and energy efficiency in AI systems," said Aveek Sarkar, director of the Ecosystem and Alliance Management Division at TSMC. "With broad collaboration on AI-based solutions, our longstanding partnership is further accelerating our mutual customers’ journey of expanding AI with leadership silicon.”

A14 Certified Tool Flows for Next-Generation Computing

Cadence's digital full flow, signoff flow, and custom/analog flows are now certified for TSMC A16™ and A14 process technologies. The digital full flow features the Innovus™ Implementation System, Cadence Cerebrus® Intelligent Chip Explorer for DTCO and enhanced signoff tools including the Tempus™ Timing and ECO Solution, EMX® Planar 3D Solver, Voltus™ IC Power Integrity Solution, Quantus™ Extraction Solution, Pegasus™ Verification System, and the Liberate™ Characterization Portfolio and the enabled Genus™ Synthesis Solution.

For custom and analog design, Virtuoso® Studio solutions include design‑rule‑correct layout generation and automated design migration to TSMC A16 and A14, reducing iterations by up to 2.5X and improving first‑pass success for AI, HPC and mobile SoCs.

On the IP front, UCIe™-64G has been taped out on TSMC A14, LPDDR6 IP is in development, and a wide selection of HPC & AI memory IP and other protocols needed for compute chiplets have been prioritized for development. Artisan® Foundation IP and mixed‑signal IP for TSMC A14 are also in development and are expected to be available in Q4 2026, including standard cells, GPIO, and Memory Compilers for HPC/AI and networking applications.

N2P Certified Tool Flows and IP for Infrastructure AI and Physical AI Applications

Cadence analog, digital, and signoff tool flows have been certified for TSMC N2P. The Virtuoso Layout Suite has added enhanced connectivity models providing a production-ready custom design environment for quicker design starts. Further, the certified flows will enable faster tape-outs and designer productivity. Taped-out N2P IP includes DDR5, LPDDR5, and PCIe 6.0, with PCIe 3.0 IP expected to tape out in Q4 2026. UCIe-64G IP on N2P silicon is in the testing lab and has been characterized on N3P.

Expanded 3DFabric® and TSMC-COUPE™ Support for Scaling to Hundreds of Chiplets

Cadence solutions are enabled supporting TSMC SoW-X full design flow with hundreds of chiplets and millions of bumps. Also enabled is the design of 5X reticle‑size CoWoS‑L‑style advanced packages, and ability to integrate key technology components such as SoIC, eDTC, MIMCap, IVR, HBM logic base die, and substrate, using Integrity 3D-IC for system planning and assembly.

A pre-simulation-driven, die-to-die auto-routing flow is now certified with the Cadence Allegro® Substrate Router and the Cadence OmniRoute Advanced Interconnect Router, automatically deriving signal-integrity-optimized routing strategies across all CoWoS® architectures and targeting UCIe requirements.

TSMC-COUPE™ (Compact Universal Photonic Engine) for high‑bandwidth photonic‑to‑silicon connectivity is enabled for integration with Cadence 224G SerDes IP. This SerDes IP is aligned with the UALink, ESUN, UltraEthernet and CPO ecosystems, complementing a complete portfolio of IP for HPC/AI applications that includes HBM4/4E, LPDDR6/5X, DDR5-MRDIMM, PCIe 7.0, and UCIe 64G.

Customer Taping Out

Global Unichip Corp. (GUC) leverages Cadence solutions to deliver advanced custom silicon for AI accelerators and hyperscale systems on TSMC's leading-edge process technologies. Cadence-driven automation helps GUC reduce schedule risk for new process technology engagements.

“As designs scale to leading‑edge TSMC process technologies such as N3P and N2P, success depends on tightly optimized execution across increasingly complex system requirements—especially when working with the early‑adopters where schedule risk is highest," said Louis Lin, senior vice president at Global Unichip Corp. “Cadence's solutions provide the predictability, performance and silicon correlation we need to successfully deliver and tape out complex designs on TSMC's most advanced nodes.”

Visit Cadence at 2026 TSMC OIP Ecosystem Forum

The innovations delivered through Cadence’s collaboration with TSMC will be showcased at the 2026 TSMC North America OIP Ecosystem Forum held on September 23 at the Santa Clara Convention Center.

About Cadence

Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence's Intelligent System Design™ strategy, are essential for the world's leading semiconductor and systems companies to build their next‑generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world's top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.

© 2026 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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Source: Cadence Design Systems, Inc.

Key Terms

ucie technical

UCIe (Universal Chiplet Interconnect Express) is an industry standard for connecting small processor or memory building blocks, called chiplets, inside a single package so they work together like parts of a single chip. For investors, it matters because it can lower manufacturing costs, speed product development, and enable more flexible, high-performance semiconductors—similar to using interchangeable Lego pieces instead of carving one large block—potentially affecting makers’ competitiveness and profit margins.

serdes technical

SerDes (short for serializer/deserializer) is an electronic function that converts parallel streams of data into a single fast serial stream and then converts it back, like packing many lanes of traffic into one high-speed highway and unpacking them at the other end. Investors care because SerDes chips and blocks determine how quickly and efficiently devices, data centers and networks can move information; improvements or bottlenecks affect product performance, production costs, and demand across the semiconductor and communications supply chain.

ppa technical

A PPA (Power Purchase Agreement) is a long-term contract in which a buyer agrees to purchase electricity from a specific generator at agreed prices and terms. Think of it like a multi-year subscription for power that locks in supply and cost, giving the seller steady revenue and the buyer predictable energy costs. Investors care because PPAs reduce revenue uncertainty, help projects get financed, and shift exposure to energy price or supply risks, affecting a company’s cash flow and valuation.

3d-ic technical

3D-IC (three-dimensional integrated circuit) is a way of building computer chips by stacking multiple silicon layers or small chips on top of one another and connecting them with tiny vertical links, like turning a stack of pancakes into a compact tower with small pipes between layers. For investors, 3D-ICs can boost speed, reduce power use and shrink product size, but they also raise manufacturing complexity, yield and capital costs, so adoption affects margins, product competitiveness and supplier relationships.