Cadence Delivers Enterprise-Level Reliability with Next-Gen Low-Power DRAM for AI Applications Featuring Microsoft RAIDDR ECC Technology

Key Terms

lpddr5x technical

LPDDR5X is a modern, low-power type of volatile memory used mostly in smartphones, tablets and other energy-sensitive devices to store working data temporarily while apps run. Think of it as a faster, more efficient short-term memory for a device — its speed and lower power use can improve performance and battery life, so adoption trends affect makers of chips and devices and can signal competitiveness in hardware design.

dram technical

A dram is a small, traditional unit used to measure either mass or liquid volume in manufacturing and pharmaceuticals — roughly 1.77 grams for a weight dram or about 3.7 milliliters for a fluid dram, similar to a small teaspoon or a couple of drops. Investors care because dram-based measurements affect drug dosing, packaging sizes, labeling compliance and raw-material usage, which in turn influence production costs, inventory counts and regulatory risk.

ecc technical

An earnings conference call (ECC) is a live audio presentation where a company’s leaders discuss recent financial results and answer questions from analysts and investors. Think of it as a post-game locker-room briefing that explains what happened, why it mattered, and what management expects next; investors listen for explanations, tone, and new details that can change the stock’s outlook.

sideband ecc technical

Sideband ECC is an error-correcting system applied to sideband communication channels—secondary signal paths that carry control, status, or management information alongside primary data links. It detects and fixes transmission errors on those auxiliary lines, similar to having a spelling-checker for a separate set of control messages. For investors, stronger sideband ECC means greater product reliability and lower risk of failures or costly recalls in devices that rely on these control channels.

rdimm technical

A RDIMM is a type of server memory module with a small built-in buffer that helps stabilize and coordinate data moving between the processor and many memory chips, making large amounts of memory more reliable and scalable. For investors, RDIMMs matter because they influence the cost, performance and reliability of data centers and enterprise hardware — factors that affect spending by cloud providers, server makers and companies that build or sell memory components, similar to how stronger building materials affect the cost and longevity of a construction project.

pci express technical

PCI Express (PCIe) is a high-speed electrical standard that links internal computer components—like graphics cards, solid-state drives and network adapters—to the processor and memory so they can rapidly exchange data. Investors care about PCIe because newer versions and wider support mean faster, more capable products and greater demand for the chips and components that use them; think of PCIe like a highway whose width and speed determine how much traffic and commerce it can carry.

ucie technical

UCIe (Universal Chiplet Interconnect Express) is an industry standard for connecting small processor or memory building blocks, called chiplets, inside a single package so they work together like parts of a single chip. For investors, it matters because it can lower manufacturing costs, speed product development, and enable more flexible, high-performance semiconductors—similar to using interchangeable Lego pieces instead of carving one large block—potentially affecting makers’ competitiveness and profit margins.

3d-ics technical

Three-dimensional integrated circuits (3D‑ICs) are semiconductor chips built by stacking multiple layers of circuitry vertically and connecting them so they act as a single, compact device. For investors, 3D‑ICs matter because they can deliver faster performance, lower power use and smaller products than traditional flat chips, but they also involve more complex manufacturing and supply‑chain risks that can affect costs, production timelines and profitability.

Industry-first LPDDR5X IP system solution designed specifically for data centers utilizes RAIDDR ECC algorithm

SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence (Nasdaq: CDNS) today announced the industry’s first LPDDR5X 9600Mbps memory IP system solution designed specifically for enterprise and data center applications with high reliability. This innovative solution integrates Cadence’s production-proven LPDDR5X IP and Microsoft’s advanced redundant array of independent double data rate (RAIDDR) error correction code (ECC) coding schema, delivering a powerful combination of high performance, low power consumption and robust reliability. Microsoft is the first customer to deploy the new system solution.

In the AI infrastructure build-out, LPDDR5X is gaining traction in the data center due to its ability to boost energy efficiency and performance for AI, HPC and other memory-intensive workloads. While LPDDR5X-based systems reduce power consumption and run times, hyperscalers have until now faced a tradeoff between power, performance and area (PPA) and the reliability, availability and serviceability (RAS) offered by DDR5 memory.

Built on LPDDR5X DRAM technology, the new memory IP system solution enables enterprise RAS capabilities while maintaining PPA in a compact form factor. The solution supports up to 9600Mbps data rates and offers sideband ECC performance comparable to traditional DDR5 ECC implementations, making it ideal for data center applications.

At the core of the solution is Microsoft’s RAIDDR ECC coding schema—a next-generation error correction algorithm that achieves close to single device data correction (SDDC), providing industry-leading accuracy and fault detection with minimal logic overhead. RAIDDR offers protection equivalent to symbol-based ECC, traditionally associated with DDR5 RDIMM-based applications.

Key features of the new memory system solution include:

• Support for 40-bit channels using LPDDR5X DRAM
• 9600Mbps performance combined with low power consumption
• Enterprise-grade RAS with DDR5-style symbol-based ECC reliability
• Sideband ECC support for maximum channel bandwidth
• Compact form factor for space-constrained systems

“Our LPDDR5X 9600Mbps system solution marks a major milestone in memory innovation for the enterprise and data center markets,” said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. “By combining the speed and power efficiency of LPDDR5X with the reliability of Microsoft’s innovative RAIDDR ECC technology, we’re delivering a solution that redefines what’s possible in high-performance, low-power memory systems.”

“Microsoft is proud to introduce RAIDDR, our next-generation enterprise DRAM symbol-based ECC algorithm, which delivers high accuracy and reliability,” said Saurabh Dighe, corporate vice president of Systems Planning and Architecture at Microsoft. “By collaborating with Cadence and using their LPDDR5X system IP, we are driving the industry’s adoption of high-performance, lower power data center solutions.”

Available as complete subsystems, Cadence’s memory IP solutions are designed for high-performance AI training and inference applications. In July 2025, Cadence introduced the industry’s first LPDDR6 memory IP system solution operating at speeds of 14.4Gbps—providing customers with a strong roadmap for future performance upgrades. Cadence offers a comprehensive portfolio of silicon-proven, PPA-optimized memory and interface IP for HPC and AI applications, including the latest versions of key industry standards such as LPDDR, HBM, DDR5, PCI Express^® (PCIe^®), Universal Chiplet Interconnect Express^™ (UCIe^™), UALink, Ultra Ethernet and high-speed Ethernet with broad solutions that include verification IP and support for chiplets, including 3D-ICs.

For more information on Cadence’s LPDDR memory solutions, please visit the LPDDR landing page.

About Cadence

Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design^™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.

© 2026 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. PCI Express and PCIe are registered trademarks of PCI-SIG. Universal Chiplet Interconnect Express and UCIe are trademarks of the UCIe Consortium. All other trademarks are the property of their respective owners.

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Source: Cadence Design Systems, Inc.