Cadence Subsystem for PCIe 6.0 Architecture Achieves First-Pass PCI Express Specification Compliance

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Complete x8 subsystem solution in TSMC N3 process demonstrates industry readiness for mass production and de-risks adoption for AI/HPC customers

SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence (Nasdaq: CDNS) today announced that its PHY and controller IP for the PCI Express^® (PCIe^®) 6.0 specification, implemented in the TSMC N3 process, achieved first-pass success at the recent PCI-SIG^® compliance workshop held in late July. The workshop marked the industry’s first official event for PCIe 6.0 specification compliance testing, with Cadence’s x8 subsystem solution tested at the full PCIe 6.0 specification speed of 64 GT/s.

The complete Cadence subsystem solution, comprising both PHY and controller, successfully passed all official PCIe 6.0 compliance specification tests and is on PCI-SIG’s Integrators List.

“PCI Express is a crucial scale-up interconnect for AI/HPC data centers and AI factories, and Cadence’s subsystem for the PCIe 6.0 specification delivers best-in-class performance with among the lowest power in the industry,” said Marc Loinaz, vice president of research and development for high-performance PHY, Silicon Solutions Group at Cadence. “This first-pass compliance success validates our complete PHY and controller solution and gives customers confidence that our technology is fully interoperable and ready for production.”

The milestone underscores the importance of early ecosystem collaboration in bringing new standards to market. Cadence worked closely with PCI-SIG, test equipment providers, and industry partners in the months leading up to the official compliance workshop, conducting interoperability testing to identify and resolve potential issues before the formal evaluation.

“As PCIe 6.0 technology enables the next wave of AI and high-performance computing systems, rigorous compliance and interoperability testing are essential for ecosystem success,” said Brig Asay, General Manager, Network Data Center, Keysight Technologies. “Cadence’s first-pass compliance achievement reflects both the quality of its PCIe 6.0 subsystem implementation and the effectiveness of comprehensive validation using Keysight’s test and measurement solutions. We are pleased to support industry leaders in accelerating PCIe 6.0 technology deployment with confidence.”

“Cadence is a long-standing PCI-SIG member helping to further PCIe technology adoption,” said Al Yanes, president and chairperson of PCI-SIG. “Cadence’s PCIe 6.0 compliance milestone plays a role in the continued advancement of PCIe technology architecture.”

PCIe 6.0 technology addresses growing demand for high-bandwidth connectivity in AI and high-performance computing systems, where the standard is used for accelerator cards, network interfaces, and storage devices. The interface is expected to see wide adoption in data center and AI infrastructure, with broader deployment in automotive and enterprise systems following as the ecosystem matures.

“Positron AI has licensed Cadence’s SerDes IP for the PCIe 6.0 specification for our AI inference accelerator chip,” said Thomas Sohmers, CTO at Positron AI. “Cadence’s complete PCIe 6.0 subsystem built in silicon and robust interoperability testing give us confidence that our PCIe 6.0 interface will meet the high-bandwidth connectivity demands of our transformer workloads.”

Key features of Cadence’s PCIe 6.0 technology solution include:

• Complete subsystem solution with PHY and controller built in silicon
• ADC and DSP-based equalization
• Firmware-optimized SerDes operation
• Multi-protocol flexibility and support
• Optimized for low power, including support for the latest PCI-SIG engineering change notices (ECNs)
• Certification for x8 configuration on TSMC N3 process

PCI-SIG has continued to advance the PCIe standard to meet the needs of advanced HPC and AI workloads. Cadence offers a broad portfolio of PCIe technology solutions up to the PCIe 7.0 specification.

Cadence’s complete subsystem solution for PCIe 6.0 technology, including PHY and controller, is available now for SoC providers to design in. For more information on Cadence IP for PCIe 6.0 technology, visit the Cadence PCIe 6.0 and CXL PHY product page or download the Design IP brochure.

About Cadence

Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2025, Cadence was recognized by Fortune as one of the world’s top 100 best companies to work for. Cadence solutions offer limitless opportunities.

Category: Featured

© 2026 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

PCI-SIG, PCI Express, and PCIe are trademarks or registered trademarks of PCI-SIG. All other trademarks are the property of their respective owners.

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Source: Cadence Design Systems, Inc.

Key Terms

serdes technical

SerDes (short for serializer/deserializer) is an electronic function that converts parallel streams of data into a single fast serial stream and then converts it back, like packing many lanes of traffic into one high-speed highway and unpacking them at the other end. Investors care because SerDes chips and blocks determine how quickly and efficiently devices, data centers and networks can move information; improvements or bottlenecks affect product performance, production costs, and demand across the semiconductor and communications supply chain.

dsp-based equalization technical

A technical method that uses digital signal processors (DSPs) to correct distortions and imbalances in electrical or optical signals by adjusting their frequency, timing and amplitude. Like using an audio equalizer or photo editor to restore clarity, DSP-based equalization improves how well a device transmits or receives data, often enabling higher speeds, longer range or fewer bulky analog components—features that can affect product performance, costs and competitiveness.

interoperability testing technical

Interoperability testing checks whether different software, devices or systems can connect and work together reliably, like testing whether new appliances fit and run on a household’s existing outlets and wiring. Investors care because successful interoperability lowers the risk of costly fixes, speeds product adoption and regulatory acceptance, and can protect revenue and market share by ensuring offerings plug smoothly into customers’ existing setups.