Rhea-AI Summary
Faraday Technology (FDYTF) announced the availability of its silicon-proven MIPI C/D Combo PHY interface IP on UMC’s 14nm FinFET process. The design supports camera and sensor connections for vision AI, machine vision and smart imaging systems. It supports MIPI C-PHY v2.0 at up to 3.0 Gsps per trio and D-PHY v2.5 at up to 4.5 Gbps per lane, with scalable configurations for different bandwidth requirements.
The two protocols share circuitry and pins. Faraday says this architecture reduces IP die area by more than 30%. The design also includes built-in self-testing for both protocols, receiver calibration for D-PHY and an Alternate Low Power mode for low-activity states.
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