Faraday Powers Intelligent Sensing with New 14nm MIPI C/D Combo PHY IP
Faraday Technology (FDYTF) announced the availability of its silicon-proven MIPI C/D Combo PHY interface IP on UMC’s 14nm FinFET process.
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Faraday Technology (FDYTF) announced the availability of its silicon-proven MIPI C/D Combo PHY interface IP on UMC’s 14nm FinFET process. The design supports camera and sensor connections for vision AI, machine vision and smart imaging systems. It supports MIPI C-PHY v2.0 at up to 3.0 Gsps per trio and D-PHY v2.5 at up to 4.5 Gbps per lane, with scalable configurations for different bandwidth requirements.
The two protocols share circuitry and pins. Faraday says this architecture reduces IP die area by more than 30%. The design also includes built-in self-testing for both protocols, receiver calibration for D-PHY and an Alternate Low Power mode for low-activity states.
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HSINCHU, Taiwan, Oct. 13, 2026 (GLOBE NEWSWIRE) -- Faraday Technology Corporation (TWSE: 3035), a leading provider of ASIC design services and IP, today announced the availability of its silicon-proven MIPI C/D Combo PHY IP on UMC’s 14nm FinFET process. The IP delivers a cost-effective, high-speed connectivity solution for vision AI, machine vision, smart imaging, and other advanced SoC applications requiring high-performance camera and sensor interfaces.
To address the growing demand for intelligent sensing, Faraday has expanded its MIPI C/D Combo PHY IP portfolio on UMC’s 14nm FinFET platform. The IP supports both MIPI C-PHY v2.0 at up to 3.0 Gsps per trio and D-PHY v2.5 at up to 4.5 Gbps per lane, featuring scalable configurations to meet diverse bandwidth requirements. By sharing pins, digital logic, I/O buffers, PLLs, and calibration circuits between both protocols, this combo architecture reduces IP die area by more than
The dual-protocol architecture enables system-level optimization by leveraging C-PHY for high-performance video transmission and D-PHY for low-power or standby operations. To enhance signal robustness during high-bandwidth data reception, the D-PHY receiver incorporates high-speed de-skew calibration. Meanwhile, built-in self-test (BIST) capabilities support both protocols, simplifying mass-production testing and reducing test costs. Furthermore, the IP features Alternate Low Power (ALP) mode, providing an additional option for reducing energy consumption during low-activity states.
“Edge AI and automotive smart sensing are driving the need for high-performance, power-efficient video connectivity,” said Flash Lin, Chief Operating Officer at Faraday Technology. “Our silicon-proven MIPI C/D Combo PHY IP enables next-generation sensing solutions with greater flexibility and efficiency. Together with our comprehensive UMC IP portfolio, Arm-based SoC integration capabilities, and ASIC expertise, Faraday helps customers simplify system development, reduce testing effort and risk, and accelerate time-to-market.”
About Faraday Technology Corporation
Faraday Technology Corporation (TWSE: 3035) is dedicated to the mission of benefiting humanity and upholding sustainable values in every IC it handles. The company offers a comprehensive range of ASIC solutions, including 2.5D/3D Advanced packaging, Arm Cortex-A, R, M, A720AE, Neoverse CSS integration and hardening, FPGA-Go-ASIC, and design implementation services. Furthermore, its extensive silicon IP portfolio encompasses a wide array of offerings, such as I/O, Cell Library, Memory Compiler, DDR/LPDDR, MIPI D-PHY, V-by-One, USB, Ethernet, SATA, PCIe, and SerDes. For further information, visit www.faraday-tech.com or follow Faraday on LinkedIn.
Press Contact
Evan Ke
+886.3.578.7888 ext. 88689
evan@faraday-tech.com
