Keysight Introduces Chiplet PHY Designer for Simulating D2D to D2D PHY IP Supporting the UCIe™ Standard

Rhea-AI Summary

Keysight Technologies introduces Chiplet PHY Designer, the industry's first EDA tool to provide in-depth modeling and simulation capabilities for verifying performance of heterogeneous and 3D integrated circuit designs. The tool simulates the UCIe specification for D2D physical layer interconnect, addressing the effects of forward clocking and higher bit error rate on die-to-die interconnect performance of chiplets. UCIe is an open standard that defines the interconnect between chiplets within an advanced 2.5D or 3D package, and is emerging as the leading chiplet interconnect specification in the semiconductor industry.

Market Research Analyst

The introduction of Keysight Technologies' Chiplet PHY Designer marks a significant advancement in the field of electronic design automation (EDA) tools, particularly for the burgeoning chiplet market. The ability to simulate die-to-die (D2D) interconnect performance is crucial as the semiconductor industry moves towards more complex, heterogeneous and 3D integrated circuit designs. The focus on ensuring compliance with the Universal Chiplet Interconnect Express (UCIe) standard underscores the industry's shift towards standardization, which could lead to broader interoperability and a more robust ecosystem for chiplet-based products.

From a market perspective, this development is poised to enhance Keysight's competitive position within the EDA market, potentially increasing its market share and revenue. The demand for chiplets is expected to grow as they enable more efficient and cost-effective scaling of computing power. Keysight's early mover advantage in providing a tool that addresses specific UCIe compliance could make it a preferred partner for semiconductor companies, thereby influencing its stock performance positively. However, the long-term impact on the company's financials will depend on the market's adoption rate of the UCIe standard and the subsequent uptake of Keysight's Chiplet PHY Designer tool.

Financial Analyst

Keysight Technologies' launch of the Chiplet PHY Designer tool represents a strategic investment into a high-growth potential market. The semiconductor industry's transition to chiplet architectures is driven by the need for greater performance and flexibility, which in turn fuels the demand for sophisticated design and simulation tools. By addressing the challenges of D2D interconnect performance and UCIe compliance, Keysight is tapping into a niche yet expanding segment that could have a positive impact on its financial performance.

Investors should note that research and development in high-speed digital interfaces and compliance with industry standards like UCIe can be capital-intensive. However, these investments can lead to high-margin products and services due to the technical expertise required, potentially improving Keysight's profitability. The success of the Chiplet PHY Designer could also lead to cross-selling opportunities with the company's existing oscilloscope and other EDA products. Monitoring the adoption of this tool by semiconductor companies will be essential in assessing its contribution to Keysight's revenue growth and overall market valuation.

Semiconductor Industry Analyst

The release of the Chiplet PHY Designer by Keysight Technologies is a pivotal development for the semiconductor industry, particularly in the context of the UCIe standard's emergence. The tool's ability to address forward clocking issues, single-ended signaling and high bit error rate challenges is indicative of the technical complexities associated with chiplet design. By providing a solution that simplifies the electrical simulation process for large D2D electrical connectivity, Keysight is facilitating the semiconductor industry's shift towards more modular and efficient integrated circuits.

Understanding the technicalities of UCIe compliance, such as voltage transfer function and bit error rate analysis, is essential for industry stakeholders. As chiplet designs become more prevalent, the performance of these interconnects becomes critical to the overall system performance. The Chiplet PHY Designer's capabilities in simulating and validating these parameters early in the design cycle can significantly reduce time-to-market for new semiconductor products. This tool could become an industry benchmark for chiplet design validation, potentially influencing the standardization process and adoption rates of chiplet technologies.

• Chiplet PHY simulator addresses the effects of forward clocking with single-ended signaling and higher bit error rate on die-to-die interconnect performance of chiplets
• Models and simulates UCIe-based compliance measures such as voltage transfer function
• Leverages Keysight EDA’s technology and history of success simulating complex physical layer standards such as SerDes and memory

SANTA ROSA, Calif.--(BUSINESS WIRE)-- Keysight Technologies, Inc. (NYSE: KEYS) introduces Chiplet PHY Designer, the latest member in its family of high speed digital design and simulation tools that provides die-to-die (D2D) interconnect simulation, which is a key step in verifying performance for heterogeneous and 3D integrated circuit (IC) designs commonly referred to as chiplets. The new electronic design automation (EDA) tool is the industry’s first to provide in-depth modeling and simulation capabilities that enable chiplet designers to rapidly and accurately verify that their designs meet specifications of the Universal Chiplet Interconnect Express™ (UCIe™) standard.

Chiplet PHY Designer simulates the UCIe specification for D2D physical layer interconnect. (Graphic: Business Wire)

UCIe is emerging as the leading chiplet interconnect specification in the semiconductor industry. It is an open standard that defines the interconnect between chiplets within an advanced 2.5D or 3D package. UCIe is in process of being supported or adopted by many of the top semiconductor equipment and EDA tool vendors as well as foundries and chiplet designers. Designers who use the interconnect standard and ensure their chiplets perform to its specifications are helping establish a broad ecosystem for chiplet interoperability and commerce.

Keysight EDA’s research and development team has been working on modeling and simulating high-speed digital interfaces aligned with industry specifications for decades. For example, ADS Memory Designer offers comprehensive memory interface coverage such as GDDR7, DDR5, LPDDR5, and HBM3 with its IBIS-AMI modeler. Its rigorous and genuine JEDEC compliance test solution handles over 100 test IDs with the same test algorithm found in the Keysight Infinium oscilloscope family.

Key features of the Chiplet PHY Designer physical-layer simulator include:

• Supports UCIe physical layer standard – automated parsing of signals following the standard naming conventions, automated connections between multiple dies through package interconnects, standard driven simulation setup such as speed grade, and intuitive measurement setup through specialized probe component.
• Measurement of voltage transfer function (VTF) – precisely computes a VTF to ensure UCIe specification compliance and analyzes system bit error rate (BER) down to 1e-27 or 1e-32 levels. Measures eye diagram height, eye width, skew, mask margin, and BER contour.
• Analysis of forwarded clocking to accurately capture the asynchronous clocking behavior.

Adrien Auge, Senior Staff Applications Engineer, Alphawave Semi, said: “The ability to validate Alphawave Semi’s chiplet solutions is crucial for enabling a future of heterogenous chip design, as it ensures seamless operation and interoperability for 2.5D/3D solutions available to our customers. Chiplet PHY Designer simplifies the electrical simulation process for large die-die electrical connectivity, such as UCIe. It provides engineers and designers a quick and easy path to extract electrical compliance of their solutions against the latest revision of the specification. Furthermore, by complying with the latest IBIS modeling specification for electrical I/O, physical integrators can delve deeper into the chiplet electrical validation process, leveraging our detailed models to obtain pre-silicon performance predictions.”

Niels Faché, Vice President and General Manager, Keysight EDA, said: “Our high-speed digital simulation team capitalized on its understanding of the shift left challenges presented by SerDes PHYS. They have applied these learnings to the chiplet domain to extend success of our standards-based simulation strategy to UCIe. Interconnect modeling is critical to system design and performance. Chiplet PHY Designer accelerates validation of chiplet subsystems, from one D2D PHY through interconnect channels to another D2D PHY, much earlier in the design cycle. It enables 3D IC designers to solve critical interconnect performance problems improving predictive virtual prototyping to speed time-to-market.”

See Chiplet PHY Designer at DesignCon
Keysight will be demonstrating Chiplet PHY Designer in its DesignCon booth #1039 at the Santa Clara Convention Center from January 31-February 1, 2024.

For more information, visit: Chiplet PHY Designer

About Keysight Technologies

At Keysight (NYSE: KEYS), we inspire and empower innovators to bring world-changing technologies to life. As an S&P 500 company, we’re delivering market-leading design, emulation, and test solutions to help engineers develop and deploy faster, with less risk, throughout the entire product lifecycle. We’re a global innovation partner enabling customers in communications, industrial automation, aerospace and defense, automotive, semiconductor, and general electronics markets to accelerate innovation to connect and secure the world. Learn more at Keysight Newsroom and www.keysight.com.

View source version on businesswire.com: https://www.businesswire.com/news/home/20240124811619/en/

Keysight Media Contacts

Paul Erwin

Americas

+1 248 430–9075

paul.erwin@keysight.com

Fusako Dohi

Asia

+81 42 660-2162

fusako_dohi@keysight.com

Jenny Gallacher

Europe

+44 (0) 7800 737 982

jenny.gallacher@keysight.com

Source: Keysight Technologies, Inc.

FAQ

What is Chiplet PHY Designer?

Chiplet PHY Designer is an EDA tool introduced by Keysight Technologies, which provides in-depth modeling and simulation capabilities for verifying performance of heterogeneous and 3D integrated circuit designs.

What does UCIe stand for?

UCIe stands for Universal Chiplet Interconnect Express, which is an open standard that defines the interconnect between chiplets within an advanced 2.5D or 3D package.

What are the key features of Chiplet PHY Designer?

The key features of Chiplet PHY Designer include support for UCIe physical layer standard, measurement of voltage transfer function, analysis of forwarded clocking, and intuitive measurement setup through specialized probe component.

What is the significance of UCIe in the semiconductor industry?

UCIe is emerging as the leading chiplet interconnect specification in the semiconductor industry, and it is being supported or adopted by many semiconductor equipment and EDA tool vendors, foundries, and chiplet designers.

What will Keysight demonstrate at DesignCon?

Keysight will be demonstrating Chiplet PHY Designer in its DesignCon booth at the Santa Clara Convention Center from January 31-February 1, 2024.