Marvell Develops Industry's First 2nm Custom SRAM for Next-Generation AI Infrastructure Silicon

Rhea-AI Summary

Marvell Technology (NASDAQ: MRVL) has introduced the industry's first 2nm custom Static Random Access Memory (SRAM), designed to enhance the performance of custom XPUs and devices for cloud data centers and AI clusters. The innovative SRAM delivers up to 6 gigabits of high-speed memory while operating at up to 3.75 GHz. Key benefits include up to 15% total die area savings and 66% reduction in on-chip memory standby power consumption. The custom SRAM achieves the industry's highest bandwidth per square millimeter, allowing chip designers to integrate more compute cores, expand memory, or reduce device size. This development is part of Marvell's broader custom technology platform strategy, which includes previous innovations like CXL technology and custom HBM technology, aimed at improving memory hierarchy performance in accelerated infrastructure.

Positive

• Achieves industry's highest bandwidth per square millimeter with up to 6 gigabits of high-speed memory
• Enables up to 15% recovery of total die area in 2nm designs
• Reduces on-chip memory standby power consumption by up to 66%
• Operates at high speeds of up to 3.75 GHz
• Provides flexibility for designers to optimize compute cores, memory, or device size

Negative

• None.

Insights

Semiconductor Technology Expert

Marvell's 2nm custom SRAM breakthrough enables significant AI chip improvements through memory efficiency, area savings, and reduced power consumption.

Marvell's announcement of the industry's first 2nm custom SRAM represents a significant technical achievement in the semiconductor space, particularly for AI infrastructure. The new technology delivers up to 6 gigabits of high-speed memory while providing 15% die area savings and reducing standby power consumption by up to 66%.

The technical implications are substantial. By achieving the highest bandwidth per square millimeter in the industry, Marvell is addressing one of the critical bottlenecks in AI chip design. The reclaimed silicon real estate gives chip designers valuable flexibility - they can add more compute cores, expand memory capacity, or reduce overall chip size and cost depending on specific application requirements.

This innovation aligns with the industry's post-Moore's Law strategy where performance gains come less from transistor scaling and more from specialized design optimizations. The 3.75 GHz operating frequency is particularly impressive for on-chip SRAM at the 2nm node.

Marvell's holistic approach to memory hierarchy optimization is noteworthy. The company has systematically addressed memory challenges at multiple levels: on-die SRAM (this announcement), package-level with custom HBM technology, and system-level with their CXL technology. This comprehensive strategy positions Marvell strongly in the custom silicon era where chip design increasingly focuses on workload-specific optimizations rather than general-purpose computing.

For AI applications specifically, memory bandwidth and capacity are critical constraints. This custom SRAM technology helps alleviate these bottlenecks while simultaneously addressing power efficiency - another major challenge in large-scale AI deployments. The technology appears particularly valuable for inference workloads where reduced latency and power consumption are paramount.

• Industry's highest bandwidth per sq mm with up to 6 gigabits of high-speed memory
• Saves up to 15% of total die area and reduces on-chip memory standby power by up to 66%
• Expands Marvell custom technology platform to transform the performance and economics of AI infrastructure

SANTA CLARA, Calif., June 17, 2025 /PRNewswire/ -- Marvell Technology, Inc. (NASDAQ: MRVL), a leader in data infrastructure semiconductor solutions expanded its custom technology platform with the launch of the industry's first 2nm custom Static Random Access Memory (SRAM), designed to boost the performance of custom XPUs and devices powering cloud data centers and AI clusters. Combining advanced custom circuitry and software from Marvell with core SRAM and cutting-edge 2nm process technology, Marvell® custom SRAM delivers up to 6 gigabits of high-speed memory while significantly reducing memory power consumption and die area at comparable densities.

Custom SRAM is the latest Marvell innovation designed to enhance memory hierarchy performance within accelerated infrastructure. Marvell previously introduced its CXL technology for integration into custom silicon to add terabytes of memory and supplemental compute capacity to cloud servers and unveiled custom HBM technology that increases memory capacity by up to 33% while reducing the space and power required for dense high-bandwidth memory (HBM) stacks inside XPUs.

Delivering the highest bandwidth per square millimeter in the industry, Marvell custom SRAM enables chip designers to recover up to 15% of the total area of a 2nm design. This recovered silicon real estate can be leveraged to integrate more compute cores, expand memory, shrink device size and cost, or achieve a tailored balance to meet specific performance power, application or TCO objectives. Built on an innovative data path and architecture, Marvell custom SRAM also consumes up to 66% less power than standard on-chip SRAM at equivalent densities, while operating at up to 3.75 GHz.

"Custom is the future of AI infrastructure. The methodologies and technologies used by hyperscalers today to develop cutting-edge custom XPUs will percolate to more customers, more classes of devices, and more applications," said Will Chu, senior vice president of Custom Cloud Solutions at Marvell. "We look forward to collaborating with our partners and customers creating the leading technology portfolio for the custom era."

"Memory remains one of the biggest challenges for AI clusters and clouds. These systems need as much memory as they can get as fast as they can," said Alan Weckel, co-founder of the 650 Group. "Marvell's holistic approach to the problem of improving memory performance at every available juncture—on the die, inside the chip package, and inside the system—is compelling and underscores the gains that become possible through customization."

A Foundation for the Custom Silicon Era

Custom SRAM is the latest extension of the Marvell custom technology platform for developing chips in a post-Moore's Law world. For over 50 years, advances in semiconductor performance and power were primarily achieved through shrinking the size of transistors. With the costs and challenges of transistor scaling increasing dramatically, semiconductor companies and their customers are customizing silicon to better serve a customer's unique infrastructure architecture, experimenting with new chip and packaging breakthroughs, and rethinking assumptions about chip design to extend the boundaries of computing.

Marvell Custom Platform Strategy

The Marvell custom platform strategy seeks to deliver breakthrough results through unique semiconductor designs and innovative approaches. By combining expertise in system and semiconductor design, advanced process manufacturing, and a comprehensive portfolio of semiconductor platform solutions and IP—including electrical and optical serializer/deserializers (SerDes), die-to-die interconnects for 2D and 3D devices, silicon photonics, co-packaged copper, custom HBM, system-on-chip (SoC) fabrics, optical IO, and compute fabric interfaces such as PCIe Gen 7— Marvell is able to create platforms in collaboration with customers that transform infrastructure performance, efficiency and value. 

About Marvell

To deliver the data infrastructure technology that connects the world, we're building solutions on the most powerful foundation: our partnerships with our customers. Trusted by the world's leading technology companies for over 25 years, we move, store, process and secure the world's data with semiconductor solutions designed for our customers' current needs and future ambitions. Through a process of deep collaboration and transparency, we're ultimately changing the way tomorrow's enterprise, cloud, automotive, and carrier architectures transform—for the better.

Marvell and the M logo are trademarks of Marvell or its affiliates. Please visit www.marvell.com for a complete list of Marvell trademarks. Other names and brands may be claimed as the property of others.

This press release contains forward-looking statements within the meaning of the federal securities laws that involve risks and uncertainties. Forward-looking statements include, without limitation, any statement that may predict, forecast, indicate or imply future events, results or achievements. Actual events, results or achievements may differ materially from those contemplated in this press release. Forward-looking statements are only predictions and are subject to risks, uncertainties and assumptions that are difficult to predict, including those described in the "Risk Factors" section of our Annual Reports on Form 10-K, Quarterly Reports on Form 10-Q and other documents filed by us from time to time with the SEC. Forward-looking statements speak only as of the date they are made. Readers are cautioned not to put undue reliance on forward-looking statements, and no person assumes any obligation to update or revise any such forward-looking statements, whether as a result of new information, future events or otherwise.

For further information, contact:
Kim Markle
pr@marvell.com

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SOURCE Marvell

FAQ

What are the key features of Marvell's new 2nm custom SRAM technology?

Marvell's 2nm custom SRAM delivers up to 6 gigabits of high-speed memory, operates at 3.75 GHz, saves up to 15% die area, and reduces power consumption by up to 66%.

How does Marvell's custom SRAM improve power efficiency?

The custom SRAM consumes up to 66% less power than standard on-chip SRAM at equivalent densities while maintaining high performance.

What benefits does Marvell's 2nm SRAM provide for chip designers?

It enables designers to recover up to 15% of total die area, which can be used to add compute cores, expand memory, reduce device size, or optimize for specific performance requirements.

How does this SRAM development fit into Marvell's broader strategy?

It's part of Marvell's custom technology platform strategy, which includes CXL and HBM technologies, aimed at improving memory hierarchy performance for AI and cloud infrastructure.

What is the significance of MRVL's 2nm SRAM for AI infrastructure?

It provides higher memory bandwidth and power efficiency crucial for AI clusters and cloud data centers, while enabling customization options for specific infrastructure needs.