Marvell Unveils Industry's First 64 Gbps/wire Bi-Directional Die-to-Die Interface IP in 2nm to Power Next Generation XPUs

Rhea-AI Summary

Marvell Technology (NASDAQ: MRVL) has unveiled the industry's first 2nm 64 Gbps bi-directional die-to-die (D2D) interconnect IP, a breakthrough technology for next-generation XPUs. The new interface delivers 32 Gbps of simultaneous two-way connectivity per wire and offers bandwidth density exceeding 30 Tbps/mm.

Key features include 3x higher bandwidth density than UCIe at equivalent speeds, 85% reduced compute die area requirements, and advanced adaptive power management that cuts power consumption by up to 75% during normal workloads. The technology, available in both 2nm and 3nm nodes, includes unique features like redundant lanes and automatic lane repair for enhanced reliability.

This announcement follows Marvell's series of 2nm innovations, including its 2nm platform announcement in March 2024 and custom SRAM technology launch.

• New D2D interface IP offers more than 3x bandwidth density of equivalent UCIe interface while requiring far less silicon
• Advanced power management capability automatically adapts to bursty data center traffic, significantly lowering power consumption
• Delivers unmatched bandwidth, efficiency, and resiliency for AI infrastructure

SANTA CLARA, Calif., Aug. 26, 2025 /PRNewswire/ -- Marvell Technology, Inc. (NASDAQ: MRVL), a leader in data infrastructure semiconductor solutions, today announced the industry's first 2nm 64 Gbps bi-directional die-to-die (D2D) interconnect, enabling chip designers to significantly boost the bandwidth and performance of next-generation XPUs while reducing power and silicon area. Delivering 32 Gbps of simultaneous two-way connectivity over a single wire, the interface IP—also available in 3nm—sets a new standard for performance, power efficiency, and resiliency to meet the scaling demands of next-generation data centers.

The Marvell^® 64 Gbps bi-directional D2D interface offers bandwidth density over 30 Tbps/mm, more than three times the bandwidth density of UCIe at equivalent speeds, and a minimal depth configuration that reduces compute die area requirements to 15% compared to conventional implementations. The interface IP is also the industry's first in its class to feature advanced adaptive power management that automatically adjusts device activity to bursty data center traffic. This innovation reduces interface power consumption by up to 75% with normal workloads and up to 42% during peak traffic periods.

The 64 Gbps bi-directional D2D interface IP also enhances performance and reliability with unique features such as redundant lanes and automatic lane repair, which improve yield and reduce bit-error rates by eliminating weak links in the system. Extending beyond the D2D PHY technology, Marvell delivers a complete solution stack—including the application bridge, link layers, and physical interconnect—providing customers with a turnkey platform to reduce time-to-market for next-generation XPUs.

"The 64 Gbps bi-directional D2D interface IP marks an industry first and reflects our commitment to pioneering technologies that enhance performance while reducing total cost of ownership for next-generation AI devices," said Will Chu, senior vice president of Custom Cloud Solutions at Marvell. "By delivering higher bandwidth at lower power, we are enabling customers to scale their architectures to meet the demands of tomorrow's accelerated computing era."

"D2D interfaces—which form the backbone of the communications networks linking silicon die within the same device--are fundamental to increasing the performance and efficiency of data center semiconductors and especially the rapidly growing custom computing segment," said Baron Fung, Senior Director of Research at Dell'Oro. "The advances achieved by Marvell are the latest step in the company's strategy to develop a portfolio of technology to accelerate the development of custom devices as well as diversify the options available to semiconductor designers."

The new 64 Gbps D2D interface technology builds on the proven Marvell track record of delivering industry firsts in advanced process technologies. In March 2024, Marvell became the first infrastructure silicon company to announce a 2nm platform. By March 2025, Marvell successfully demonstrated working 2nm silicon, followed shortly by the unveiling of its 2nm custom SRAM technology. Today's introduction of the industry's first 64 Gbps D2D interface in 2nm and 3nm nodes continues this momentum, underscoring Marvell as a leader in innovative solutions that define the future of accelerated infrastructure.

Marvell Custom Strategy
The Marvell custom platform strategy seeks to deliver breakthrough results through unique semiconductor designs and innovative approaches. By combining expertise in system and semiconductor design, advanced process manufacturing, and a comprehensive portfolio of semiconductor platform solutions and IP—including electrical and optical serializer/deserializers (SerDes), die-to-die interconnects for 2D and 3D devices, silicon photonics, co-packaged copper, custom HBM, system-on-chip (SoC) fabrics, advanced packaging, optical I/O, and compute fabric interfaces such as PCIe Gen 7— Marvell is able to create platforms in collaboration with customers that transform infrastructure performance, efficiency and value.

About Marvell
To deliver the data infrastructure technology that connects the world, we're building solutions on the most powerful foundation: our partnerships with our customers. Trusted by the world's leading technology companies for over 30 years, we move, store, process and secure the world's data with semiconductor solutions designed for our customers' current needs and future ambitions. Through a process of deep collaboration and transparency, we're ultimately changing the way tomorrow's enterprise, cloud, automotive, and carrier architectures transform—for the better.

Marvell and the M logo are trademarks of Marvell or its affiliates. Please visit www.marvell.com for a complete list of Marvell trademarks. Other names and brands may be claimed as the property of others.

This press release contains forward-looking statements within the meaning of the federal securities laws that involve risks and uncertainties. Forward-looking statements include, without limitation, any statement that may predict, forecast, indicate or imply future events, results or achievements. Actual events, results or achievements may differ materially from those contemplated in this press release. Forward-looking statements are only predictions and are subject to risks, uncertainties and assumptions that are difficult to predict, including those described in the "Risk Factors" section of our Annual Reports on Form 10-K, Quarterly Reports on Form 10-Q and other documents filed by us from time to time with the SEC. Forward-looking statements speak only as of the date they are made. Readers are cautioned not to put undue reliance on forward-looking statements, and no person assumes any obligation to update or revise any such forward-looking statements, whether as a result of new information, future events or otherwise.

Media
Kim Markle
pr@marvell.com 

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SOURCE Marvell

FAQ

What is Marvell's new 64 Gbps D2D interface technology and why is it significant?

Marvell's new technology is the industry's first 2nm 64 Gbps bi-directional die-to-die interconnect, delivering 32 Gbps of simultaneous two-way connectivity per wire. It's significant for enabling higher performance and efficiency in next-generation XPUs with 3x higher bandwidth density than current solutions.

How much power reduction does Marvell's new D2D interface achieve?

The interface achieves up to 75% power reduction during normal workloads and up to 42% reduction during peak traffic periods through its advanced adaptive power management system.

What are the key advantages of MRVL's new D2D interface over existing solutions?

The key advantages include 30+ Tbps/mm bandwidth density (3x higher than UCIe), 85% reduced compute die area, advanced power management, and enhanced reliability features like redundant lanes and automatic lane repair.

When did Marvell announce its 2nm platform and what progress has been made?

Marvell announced its 2nm platform in March 2024, demonstrated working 2nm silicon by March 2025, and subsequently launched its custom SRAM technology, showing consistent progress in 2nm innovation.