Marvell Unveils Industry's First 64 Gbps/wire Bi-Directional Die-to-Die Interface IP in 2nm to Power Next Generation XPUs
Marvell Technology (NASDAQ: MRVL) has unveiled the industry's first 2nm 64 Gbps bi-directional die-to-die (D2D) interconnect IP, a breakthrough technology for next-generation XPUs. The new interface delivers 32 Gbps of simultaneous two-way connectivity per wire and offers bandwidth density exceeding 30 Tbps/mm.
Key features include 3x higher bandwidth density than UCIe at equivalent speeds, 85% reduced compute die area requirements, and advanced adaptive power management that cuts power consumption by up to 75% during normal workloads. The technology, available in both 2nm and 3nm nodes, includes unique features like redundant lanes and automatic lane repair for enhanced reliability.
This announcement follows Marvell's series of 2nm innovations, including its 2nm platform announcement in March 2024 and custom SRAM technology launch.
Marvell Technology (NASDAQ: MRVL) ha presentato il primo IP di interconnessione die-to-die (D2D) bidirezionale a 2nm e 64 Gbps del settore, una tecnologia rivoluzionaria per le prossime XPUs. La nuova interfaccia offre 32 Gbps di connettività bidirezionale simultanea per filo e una densità di larghezza di banda superiore a 30 Tbps/mm.
Le caratteristiche principali includono una densità di banda 3x superiore rispetto a UCIe a parità di velocità, la riduzione del 85% dell'area richiesta dal die di calcolo e un avanzato sistema di gestione adattiva dell'energia che riduce il consumo fino al 75% durante i carichi di lavoro normali. La tecnologia, disponibile sia a 2nm sia a 3nm, integra funzionalità esclusive come lane ridondanti e riparazione automatica delle lane per una maggiore affidabilità.
Questo annuncio fa seguito alla serie di innovazioni a 2nm di Marvell, incluse la presentazione della piattaforma a 2nm nel marzo 2024 e il lancio della tecnologia SRAM personalizzata.
Marvell Technology (NASDAQ: MRVL) ha presentado la primera IP de interconexión die-to-die (D2D) bidireccional de 2nm y 64 Gbps de la industria, una tecnología innovadora para las próximas XPUs. La nueva interfaz ofrece 32 Gbps de conectividad bidireccional simultánea por cable y proporciona una densidad de ancho de banda superior a 30 Tbps/mm.
Las características clave incluyen una densidad de ancho de banda 3x mayor que UCIe a velocidades equivalentes, una reducción del 85% en el área necesaria del die de cómputo y una avanzada gestión adaptativa de energía que reduce el consumo hasta en un 75% durante cargas de trabajo normales. La tecnología, disponible en nodos de 2nm y 3nm, incorpora funciones únicas como carriles redundantes y reparación automática de carriles para mayor fiabilidad.
Este anuncio sigue a la serie de innovaciones de Marvell en 2nm, incluida la presentación de su plataforma de 2nm en marzo de 2024 y el lanzamiento de su tecnología SRAM personalizada.
Marvell Technology (NASDAQ: MRVL)는 업계 최초의 2nm 64Gbps 양방향 다이-투-다이(D2D) 인터커넥트 IP를 공개했으며, 이는 차세대 XPU를 위한 획기적인 기술입니다. 새로운 인터페이스는 와이어당 동시 양방향 연결에서 32Gbps를 제공하며, 대역폭 밀도는 30Tbps/mm를 초과합니다.
주요 특징으로는 동일 속도에서 UCIe보다 3배 높은 대역폭 밀도, 컴퓨트 다이 면적 요구사항의 85% 감소, 일상적인 워크로드에서 전력 소비를 최대 75%까지 절감하는 고급 적응형 전력 관리가 포함됩니다. 해당 기술은 2nm 및 3nm 공정으로 제공되며, 중복 레인과 자동 레인 복구 같은 고유 기능을 포함해 신뢰성을 향상시킵니다.
이번 발표는 2024년 3월의 2nm 플랫폼 발표와 맞춤형 SRAM 기술 출시를 포함한 Marvell의 일련의 2nm 혁신에 이은 것입니다.
Marvell Technology (NASDAQ: MRVL) a dévoilé la première IP d'interconnexion die-to-die (D2D) bidirectionnelle 2nm 64 Gbps de l'industrie, une technologie révolutionnaire pour les prochaines XPU. La nouvelle interface offre 32 Gbps de connectivité bidirectionnelle simultanée par fil et propose une densité de bande passante supérieure à 30 Tbps/mm.
Parmi les caractéristiques clés figurent une densité de bande 3x supérieure à UCIe à vitesses équivalentes, une réduction de 85% de la surface nécessaire pour la puce de calcul, et une gestion adaptative avancée de la puissance qui réduit la consommation jusqu'à 75% lors des charges de travail normales. La technologie, disponible en nœuds 2nm et 3nm, inclut des fonctionnalités uniques telles que des voies redondantes et la réparation automatique des voies pour une fiabilité accrue.
Cette annonce fait suite à la série d'innovations 2nm de Marvell, y compris l'annonce de sa plateforme 2nm en mars 2024 et le lancement de sa technologie SRAM personnalisée.
Marvell Technology (NASDAQ: MRVL) hat das branchenweit erste 2nm 64 Gbps bidirektionale Die-to-Die (D2D) Interconnect-IP vorgestellt – eine bahnbrechende Technologie für die nächste XPU-Generation. Die neue Schnittstelle liefert pro Leiter 32 Gbps gleichzeitige Zwei-Wege-Konnektivität und bietet eine Bandbreitendichte von über 30 Tbps/mm.
Wesentliche Merkmale sind eine 3x höhere Bandbreitendichte als UCIe bei gleichen Geschwindigkeiten, eine um 85% reduzierte Fläche des Compute-Die sowie ein fortschrittliches adaptives Energiemanagement, das den Stromverbrauch bei normalen Workloads um bis zu 75% senkt. Die Technologie ist sowohl in 2nm- als auch 3nm-Knoten verfügbar und enthält einzigartige Funktionen wie redundante Lanes und automatische Lane-Reparatur zur Erhöhung der Zuverlässigkeit.
Die Ankündigung folgt Marvells Reihe von 2nm-Innovationen, darunter die Vorstellung der 2nm-Plattform im März 2024 und die Einführung einer maßgeschneiderten SRAM-Technologie.
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Insights
Marvell's groundbreaking 2nm D2D interface technology gives it competitive edge in AI chip connectivity, significantly advancing XPU capabilities.
Marvell's announcement of the industry's first 64 Gbps bi-directional die-to-die (D2D) interface in 2nm technology represents a significant engineering breakthrough that addresses critical bottlenecks in AI infrastructure. This technology enables 32 Gbps of simultaneous two-way connectivity over a single wire, delivering bandwidth density over 30 Tbps/mm – more than three times the density of equivalent UCIe interfaces.
What makes this development particularly noteworthy is the 75% power reduction during normal workloads through adaptive power management that responds to bursty data center traffic patterns. The minimal depth configuration reduces compute die area requirements to just 15% compared to conventional implementations – a crucial advantage in the space-constrained world of advanced semiconductors.
The technical innovations extend beyond just raw performance metrics. The redundant lanes and automatic lane repair capabilities enhance yield and reliability by eliminating weak links, which translates to better economics for chip manufacturers. Moreover, Marvell's provision of a complete solution stack from PHY technology to application bridges gives customers a turnkey platform that accelerates time-to-market.
This development continues Marvell's aggressive push into advanced nodes, following their March 2024 announcement as the first infrastructure silicon company with a 2nm platform, and their subsequent demonstration of working 2nm silicon and custom SRAM technology. For system architects designing next-generation XPUs for AI acceleration, this interconnect technology removes a critical data movement constraint while simultaneously addressing power efficiency concerns that have become paramount in data center environments.
- New D2D interface IP offers more than 3x bandwidth density of equivalent UCIe interface while requiring far less silicon
- Advanced power management capability automatically adapts to bursty data center traffic, significantly lowering power consumption
- Delivers unmatched bandwidth, efficiency, and resiliency for AI infrastructure
The Marvell® 64 Gbps bi-directional D2D interface offers bandwidth density over 30 Tbps/mm, more than three times the bandwidth density of UCIe at equivalent speeds, and a minimal depth configuration that reduces compute die area requirements to
The 64 Gbps bi-directional D2D interface IP also enhances performance and reliability with unique features such as redundant lanes and automatic lane repair, which improve yield and reduce bit-error rates by eliminating weak links in the system. Extending beyond the D2D PHY technology, Marvell delivers a complete solution stack—including the application bridge, link layers, and physical interconnect—providing customers with a turnkey platform to reduce time-to-market for next-generation XPUs.
"The 64 Gbps bi-directional D2D interface IP marks an industry first and reflects our commitment to pioneering technologies that enhance performance while reducing total cost of ownership for next-generation AI devices," said Will Chu, senior vice president of Custom Cloud Solutions at Marvell. "By delivering higher bandwidth at lower power, we are enabling customers to scale their architectures to meet the demands of tomorrow's accelerated computing era."
"D2D interfaces—which form the backbone of the communications networks linking silicon die within the same device--are fundamental to increasing the performance and efficiency of data center semiconductors and especially the rapidly growing custom computing segment," said Baron Fung, Senior Director of Research at Dell'Oro. "The advances achieved by Marvell are the latest step in the company's strategy to develop a portfolio of technology to accelerate the development of custom devices as well as diversify the options available to semiconductor designers."
The new 64 Gbps D2D interface technology builds on the proven Marvell track record of delivering industry firsts in advanced process technologies. In March 2024, Marvell became the first infrastructure silicon company to announce a 2nm platform. By March 2025, Marvell successfully demonstrated working 2nm silicon, followed shortly by the unveiling of its 2nm custom SRAM technology. Today's introduction of the industry's first 64 Gbps D2D interface in 2nm and 3nm nodes continues this momentum, underscoring Marvell as a leader in innovative solutions that define the future of accelerated infrastructure.
Marvell Custom Strategy
The Marvell custom platform strategy seeks to deliver breakthrough results through unique semiconductor designs and innovative approaches. By combining expertise in system and semiconductor design, advanced process manufacturing, and a comprehensive portfolio of semiconductor platform solutions and IP—including electrical and optical serializer/deserializers (SerDes), die-to-die interconnects for 2D and 3D devices, silicon photonics, co-packaged copper, custom HBM, system-on-chip (SoC) fabrics, advanced packaging, optical I/O, and compute fabric interfaces such as PCIe Gen 7— Marvell is able to create platforms in collaboration with customers that transform infrastructure performance, efficiency and value.
About Marvell
To deliver the data infrastructure technology that connects the world, we're building solutions on the most powerful foundation: our partnerships with our customers. Trusted by the world's leading technology companies for over 30 years, we move, store, process and secure the world's data with semiconductor solutions designed for our customers' current needs and future ambitions. Through a process of deep collaboration and transparency, we're ultimately changing the way tomorrow's enterprise, cloud, automotive, and carrier architectures transform—for the better.
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Kim Markle
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