ASE has unveiled a groundbreaking co-packaged optics (CPO) device that directly mounts optical engines onto a substrate, achieving <5pJ/bit power consumption and significant bandwidth improvements. This innovation addresses critical data center challenges amid surging AI demands. The CPO technology demonstrates substantial efficiency gains compared to current solutions, reducing power consumption from 30pJ/bit (faceplate-pluggable) and 20pJ/bit (on-board) to less than 5pJ/bit. According to IDC, AI silicon in data centers will see 24.9% CAGR from 2024-2028. The technology enables shorter electrical paths, lower insertion loss, and improved power efficiency in packages >75mm X 75mm. McKinsey projects data center capacity demand to grow at 27% CAGR from 2023-2030, reaching 298 GigaWatts, up from current 60 GW.
[
"Achieved <5pJ/bit power consumption, significantly lower than current solutions (30pJ/bit for FPP, 20pJ/bit for on-board)",
"Technology addresses growing AI-driven data center demands with 24.9% CAGR projected from 2024-2028",
"Enables improved bandwidth, lower latency, and better data throughput",
"Solves assembly challenges for large body configurations (>75mm X 75mm)",
"Positions ASE to capitalize on projected 27% CAGR in data center capacity demand (2023-2030)"
]
ASE ha presentato un dispositivo rivoluzionario di ottica co-impacchettata (CPO) che monta direttamente i motori ottici su un substrato, raggiungendo un consumo energetico inferiore a 5pJ/bit e miglioramenti significativi nella larghezza di banda. Questa innovazione risponde alle sfide critiche dei data center in un contesto di crescente domanda di AI. La tecnologia CPO dimostra notevoli guadagni di efficienza rispetto alle soluzioni attuali, riducendo il consumo energetico da 30pJ/bit (faceplate-pluggable) e 20pJ/bit (on-board) a meno di 5pJ/bit. Secondo IDC, il silicio AI nei data center crescerà con un CAGR del 24,9% dal 2024 al 2028. La tecnologia consente percorsi elettrici più brevi, minori perdite di inserzione e migliore efficienza energetica in package superiori a 75mm X 75mm. McKinsey prevede che la domanda di capacità dei data center crescerà con un CAGR del 27% dal 2023 al 2030, raggiungendo 298 GigaWatt, rispetto agli attuali 60 GW.
ASE ha presentado un dispositivo innovador de óptica coempaquetada (CPO) que monta directamente motores ópticos sobre un sustrato, logrando un consumo de energía inferior a 5pJ/bit y mejoras significativas en el ancho de banda. Esta innovación aborda desafíos críticos en centros de datos ante la creciente demanda de IA. La tecnología CPO demuestra ganancias sustanciales en eficiencia en comparación con las soluciones actuales, reduciendo el consumo de energía de 30pJ/bit (faceplate-pluggable) y 20pJ/bit (on-board) a menos de 5pJ/bit. Según IDC, el silicio de IA en centros de datos tendrá un CAGR del 24,9% entre 2024 y 2028. La tecnología permite caminos eléctricos más cortos, menor pérdida por inserción y mejor eficiencia energética en paquetes mayores a 75mm X 75mm. McKinsey proyecta que la demanda de capacidad en centros de datos crecerá a un CAGR del 27% entre 2023 y 2030, alcanzando 298 GigaWatts, frente a los actuales 60 GW.
ASE는 광학 엔진을 기판에 직접 장착하는 획기적인 공동 패키지 광학(CPO) 장치를 공개했으며, 5pJ/비트 미만의 전력 소비와 대역폭 향상을 달성했습니다. 이 혁신은 급증하는 AI 수요 속에서 데이터 센터의 주요 과제를 해결합니다. CPO 기술은 기존 솔루션 대비 전력 소비를 30pJ/비트(페이스플레이트 플러그형) 및 20pJ/비트(온보드)에서 5pJ/비트 미만으로 크게 줄여 효율성을 크게 향상시켰습니다. IDC에 따르면 데이터 센터 내 AI 실리콘은 2024년부터 2028년까지 연평균 성장률 24.9%를 보일 전망입니다. 이 기술은 75mm X 75mm 이상의 패키지에서 전기 경로 단축, 삽입 손실 감소, 전력 효율성 향상을 가능하게 합니다. McKinsey는 데이터 센터 용량 수요가 2023년부터 2030년까지 연평균 27% 성장해 현재 60GW에서 298GW에 이를 것으로 예상합니다.
ASE a dévoilé un dispositif révolutionnaire d'optique co-emballée (CPO) qui monte directement les moteurs optiques sur un substrat, atteignant une consommation d'énergie inférieure à 5pJ/bit et des améliorations significatives de la bande passante. Cette innovation répond aux défis critiques des centres de données face à la demande croissante en IA. La technologie CPO démontre des gains d'efficacité substantiels par rapport aux solutions actuelles, réduisant la consommation d'énergie de 30pJ/bit (faceplate-pluggable) et 20pJ/bit (on-board) à moins de 5pJ/bit. Selon IDC, le silicium IA dans les centres de données connaîtra un TCAC de 24,9% entre 2024 et 2028. La technologie permet des chemins électriques plus courts, une perte d'insertion réduite et une meilleure efficacité énergétique dans des boîtiers de plus de 75mm X 75mm. McKinsey prévoit que la demande en capacité des centres de données croîtra à un TCAC de 27% entre 2023 et 2030, atteignant 298 Gigawatts, contre 60 GW actuellement.
ASE hat ein bahnbrechendes Co-Packaged Optics (CPO)-Gerät vorgestellt, das optische Module direkt auf einem Substrat montiert und dabei einen Stromverbrauch von unter 5pJ/Bit sowie erhebliche Bandbreitenverbesserungen erzielt. Diese Innovation adressiert kritische Herausforderungen in Rechenzentren angesichts der steigenden KI-Nachfrage. Die CPO-Technologie zeigt deutliche Effizienzsteigerungen im Vergleich zu aktuellen Lösungen, indem der Stromverbrauch von 30pJ/Bit (Faceplate-Pluggable) und 20pJ/Bit (On-Board) auf unter 5pJ/Bit reduziert wird. Laut IDC wird der AI-Siliziumanteil in Rechenzentren von 2024 bis 2028 mit einem CAGR von 24,9% wachsen. Die Technologie ermöglicht kürzere elektrische Wege, geringere Einfügedämpfung und verbesserte Energieeffizienz in Gehäusen größer als 75mm x 75mm. McKinsey prognostiziert, dass die Nachfrage nach Rechenzentrumskapazitäten von 2023 bis 2030 mit einem CAGR von 27% wächst und 298 Gigawatt erreicht, verglichen mit derzeit 60 GW.
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Insights
ASE's new co-packaged optics technology delivers dramatic power efficiency gains for data centers, positioning them well in the AI-driven semiconductor market.
ASE has achieved a significant technological breakthrough with their new co-packaged optics (CPO) device that mounts optical engines directly onto substrates. The innovation delivers power consumption below 5pJ/bit, representing a dramatic improvement over current faceplate-pluggable solutions (30pJ/bit) and on-board options (20pJ/bit).
This advancement addresses critical bottlenecks in data center infrastructure at precisely the right moment. With IDC projecting 24.9% CAGR for AI silicon in data centers from 2024-2028, and McKinsey forecasting data center capacity demand growing at 27% CAGR to reach 298 GW by 2030, power efficiency has become a paramount concern.
The technical achievement is particularly noteworthy as it solves complex assembly challenges for multiple optical engines with ASICs in large integrated packages exceeding 75mm × 75mm. This enables shorter electrical paths, lower insertion loss, and superior power efficiency while maintaining structural integrity for both edge and surface fiber coupling.
ASE's CPO technology offers compelling advantages across multiple dimensions:
Enables bandwidth expansion critical for AI workloads
Reduces latency in data center operations
Improves scalability compared to current optical solutions
Potentially replaces pluggable optics at 1.6Tb/s or 3.2Tb/s speeds
Provides integration options for CPUs, GPUs and other processors
Part of ASE's VIPack™ platform, this development represents an interim step in their progression toward fully integrated 3D CPO. By addressing the data center sector's urgent power constraints with next-generation packaging technology, ASE is positioning itself advantageously in the semiconductor ecosystem as AI deployments accelerate power consumption concerns.
SUNNYVALE, Calif.--(BUSINESS WIRE)--
Advanced Semiconductor Engineering, Inc. (ASE), a member of ASE Technology Holding Co., Ltd. (NYSE: ASX, TAIEX: 3711), today announced that it has demonstrated a co-packaged optics (CPO) device that mounts multiple optical engines (OE) directly onto a substrate, enabling <5pJ/bit power consumption and significant bandwidth increases. With today’s processing power requirements being extremely amplified by AI pervasion, there is unprecedented demand for bandwidth that must be addressed. ASE’s new configuration enables crucial on-package energy efficiency and bandwidth expansion while addressing further data center challenges by delivering improvement related to latency, data throughput, and scalability.
According to IDC (Jan 2025), the proliferation of AI silicon in the data center will experience 24.9% CAGR from 2024 to 2028 in support of capacity demand and infrastructure growth, hence elevating the need for new energy efficiencies. Advanced packaging creativity is bringing the OE directly into the switch silicon package to generate the shortest possible electrical traces resulting in consequential power savings. ASE’s configuration results in shorter electrical path and lower insertion loss, as well as improved power efficiency. The CPO structure is a key interim step in ASE’s progression from pluggable options to optical IO and fully integrated 3D CPO. A major milestone for ASE has been the development of the CPO assembly process flow, which includes substrate warpage and coplanarity control to meet fiber array coupling requirements, and structure and warpage synergy for both edge (horizontal) and surface (vertical) fiber coupling. All these areas are critical to ensuring optimized data throughput while minimizing optical related losses.
As bandwidth demands grow exponentially, the current faceplate-pluggable (FPP) solutions show roadmap limitations in density, power, and cost. The increasing switch speeds also lead to an increase in SerDes interconnect power as a percentage of the total switch power. This is driving the need to move the optics from the FPP into the enclosure closer to the switch ASIC. On-board optics have been adopted as a first step, and ASE’s CPO provides an attractive option that has lower insertion loss, resulting in reduced power consumption and cost/bit. From a pJ/bit comparison, FPP solutions are currently 30pJ/bit, while on-board solutions are 20pJ/bit, but now scaling <5pJ/bit through CPO.
ASE’s CPO solves the assembly challenge of multiple optical engines with an ASIC in an integrated package with a large body configuration of >75mm X 75mm. The benefits for both the networking and data center markets are significant. For networking, it provides a potential option to improve or replace pluggable optics at 1.6Tb/s or 3.2 Tb/s, as well as an integration solution that enables ultra-low latency option for CPO. For compute, the platform can be used to integrate the CPUs, GPUs, XPUs with the optics into a single co-packaged solution through high-speed optical data links.
“Global demand for data center capacity could rise at 27% CAGR from 2023 to 2030 to reach an annual demand of 298 GigaWatts (GW), according to 2025 report from McKinsey. Such tremendous growth represents a sharp increase from the current demand of 60 GW and signals a potential supply gap. This is why ASE is committed to bring power efficiencies to the data center though our CPO innovation,” said Dr. CP Hung, Vice President of Research & Development, ASE. “It’s well documented that the main driving force for CPO technology is its ability to lower energy consumption and deliver economic advantage. Our CPO places the optical engine very close to the ASIC chip, meaning link loss is reduced and there is no need for a re-timer chip to compensate for the signal between the two. This leads to significant reduction of its energy consumption, and a big improvement in the overall bandwidth density of the system.”
“Our industry has moved beyond classical compute into the high-performance compute era where data center demands are being highly influenced by advanced AI models and applications, power consumption, and ongoing cloud and edge compute dynamics,” added Yin Chang, Executive Vice President, ASE. “These present massive challenges, particularly related to power and cooling limitations, and require our industry to deliver breakthrough innovations that facilitate application and scale. At ASE, we are committed to taking silicon photonics to a new level and augmenting our customer value through delivering CPO technology that demonstrates superior energy efficiency at this critical juncture in AI permeation.”
ASE’s CPO is part of VIPack™, which is a scalable platform expanding in alignment with industry roadmaps, and supported by its Integrated Design Ecosystem™ (IDE), a collaborative design toolset optimized to systematically boost advanced package architecture.
ASE will be represented at the Optical Fiber Conference 2025 in San Francisco this week by Dr. CP Hung, VP of R&D, who will deliver a presentation titled, ‘Latest Advanced Packaging Solutions for AI’, scheduled for Thursday, April 3rd 15:15 - 15:45 in the Packaging and Coupling Techniques session.
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About ASE, Inc.
ASE, Inc. is the leading global provider of semiconductor manufacturing services in assembly and test. Alongside a broad portfolio of established assembly and test technologies, ASE is also delivering innovative VIPack™, advanced packaging, and system-in-package solutions to meet growth momentum across a broad range of end markets, including AI, Automotive, 5G, High-Performance Computing, and more. To learn about our advances in SiP, Fanout, MEMS & Sensor, Flip Chip, and 2.5D, 3D & TSV technologies, all ultimately geared towards applications to improve lifestyle and efficiency, please visit: aseglobal.com or follow us on LinkedIn & X: @aseglobal.
What is ASE's new co-packaged optics (CPO) technology and how does it improve power efficiency?
ASE's CPO technology mounts optical engines directly onto a substrate, reducing power consumption to <5pJ/bit compared to current solutions (30pJ/bit for FPP, 20pJ/bit for on-board). It achieves this through shorter electrical paths and lower insertion loss.
What market growth potential exists for ASE's (NYSE: ASX) CPO technology in data centers?
According to McKinsey, global data center capacity demand is projected to grow at 27% CAGR from 2023-2030, reaching 298 GigaWatts from current 60 GW, while AI silicon in data centers will see 24.9% CAGR from 2024-2028.
What are the key benefits of ASE's CPO technology for networking and data centers?
The technology improves or replaces pluggable optics at 1.6Tb/s or 3.2 Tb/s, enables ultra-low latency, and allows integration of CPUs, GPUs, and XPUs with optics into a single co-packaged solution through high-speed optical data links.
What technical specifications does ASE's new CPO device support?
The CPO device supports large body configurations of >75mm X 75mm, features substrate warpage and coplanarity control for fiber array coupling, and enables both edge (horizontal) and surface (vertical) fiber coupling.
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