Synopsys Inc - SNPS STOCK NEWS

Synopsys (SNPS) has announced an expanded collaboration with TSMC to deliver advanced EDA and IP solutions for TSMC's cutting-edge processes. The partnership focuses on certified digital and analog flows for TSMC A16™ and N2P processes, powered by Synopsys.ai.

Key developments include early collaboration on TSMC A14 process, support for 3Dblox and TSMC's CoWoS® technologies enabling 5.5x reticle size packages, and a comprehensive IP portfolio offering the lowest power consumption on TSMC's N2/N2P processes. The collaboration features complete IP solutions for advanced standards like HBM4, 1.6T Ethernet, UCIe, PCIe 7.0, and UALink.

The partnership enhances 3DIC Compiler capabilities, supporting ultra-high-density interconnects and increased productivity for multi-die designs. The solution integrates multi-physics analysis and Ansys simulation technologies for comprehensive power, thermal, and signal integrity analysis.

Synopsys (SNPS) announced significant advancements in chip design acceleration through collaboration with NVIDIA, showcasing up to 30x projected performance gains using the NVIDIA Grace Blackwell platform. The announcement, made at the GTC global AI conference, highlights optimization across multiple Synopsys solutions:

- Circuit Simulation: PrimeSim SPICE workloads projected to achieve 30x speedup
- Computational Lithography: Proteus software expected to accelerate simulations by up to 20x
- TCAD Simulation: Sentaurus solution projected to accelerate results up to 10x
- Materials Engineering: QuantumATK delivering up to 100x faster results

The company is expanding support for NVIDIA Grace CPU architecture, enabling more than 15 Synopsys solutions in 2025. Additionally, the integration of NVIDIA NIM inference microservices with Synopsys.ai Copilot is projected to enable 2x faster time-to-information in generative AI-powered chip design.

Synopsys (SNPS) announced its annual SNUG Silicon Valley conference, scheduled for March 19-20, 2025, at the Santa Clara Convention Center. The event will feature high-profile keynotes from industry leaders, including Synopsys CEO Sassine Ghazi and a virtual appearance by Microsoft CEO Satya Nadella discussing 'Re-engineering Engineering.'

The conference includes a fireside chat between Arm CEO Rene Haas and Ghazi on 'Sustainable Computing,' and a keynote by OpenAI's Head of Hardware Richard Ho on 'Scaling Computing for the Age of Intelligence.' The event will host over 100 sessions with presentations from major tech companies including AWS, GlobalFoundries, Microsoft, Samsung, and TSMC.

A new addition this year is the invite-only Synopsys Executive Forum on March 19, bringing together leaders from prominent companies like AMD, Intel, Meta, NVIDIA, and others to discuss silicon and systems design challenges.

Synopsys (SNPS) and Vector Informatik have announced a strategic collaboration to accelerate software-defined vehicle (SDV) development. The partnership aims to deliver pre-integrated solutions combining Vector's software factory expertise with Synopsys' electronics digital twins capabilities.

The collaboration focuses on enabling automotive companies to 'shift-left' software validation and improve developer productivity through:

• Advancement of the open-source library SIL Kit for vehicle-level digital twins
• Integration of Vector's MICROSAR embedded software and CANoe with Synopsys Silver and Virtualizer Development Kits (VDKs)
• Creation of ready-to-use virtual electronic control units (vECUs) for SDV architecture

The joint solution addresses increasing software complexity in automotive development, supports more vehicle platforms and variants, and aims to reduce development costs while enhancing software quality from early compliance verification to over-the-air updates.

Synopsys (SNPS) has announced the launch of Virtualizer Native Execution on Arm-based hardware, a significant advancement in software development for edge devices. This innovation accelerates virtual prototype execution and deployment, particularly benefiting the automotive, high-performance computing (HPC), and Internet of Things (IoT) sectors.

The solution leverages instruction set architectures (ISAs) between Arm-based servers and edge devices, enabling faster software development through common toolchains and integration into CI/CD pipelines. Key benefits include significantly increased simulation execution speeds, early software development capabilities through extensive model libraries, and accelerated application-level performance analysis through hybrid prototyping with Synopsys ZeBu systems.

The platform supports various Arm-based infrastructures including Ampere, AWS, Google, Microsoft, and Nvidia, allowing developers to optimize compute resources either in the cloud or on-premise. The solution is immediately available and aims to transform product development from silicon to systems.

Synopsys (SNPS) has received Phase 1 clearance from the U.K. Competition and Markets Authority (CMA) for its proposed acquisition of Ansys, subject to previously announced divestitures. The company continues to work on securing regulatory approvals in other jurisdictions and maintains its expectation to close the transaction in the first half of 2025.

Synopsys president and CEO Sassine Ghazi highlighted customer support for the pending acquisition, emphasizing that the merger will enable the development of new AI-powered design solutions combining electronics and physics capabilities to enhance R&D innovation.

Synopsys (SNPS) reported Q1 FY2025 results with revenue of $1.455 billion, slightly down from $1.511 billion in Q1 FY2024 but exceeding guidance midpoint. GAAP earnings were $1.89 per diluted share (net income $295.7M), compared to $2.82 (net income $437.5M) year-over-year. Non-GAAP earnings reached $3.03 per share (net income $473.2M), versus $3.38 (net income $525.5M) in Q1 FY2024.

The company reaffirmed its full-year 2025 guidance, expecting double-digit revenue growth. Following the sale of its Software Integrity business on September 30, 2024, Synopsys now operates through two segments: Design Automation and Design IP. The company highlighted strong design activity at advanced nodes and expanded generative AI capabilities in EDA.

Synopsys (SNPS) and the SEMI Foundation have signed a Memorandum of Understanding to address workforce development in the semiconductor chip design sector. The collaboration aims to tackle the predicted need for over one million additional semiconductor jobs by 2030, equivalent to 100,000 jobs annually.

The partnership will focus on developing education and training programs with academic institutions and industry experts, targeting K-12 students, academic institutions, and military veterans. Through Synopsys' SARA (Synopsys Academic & Research Alliances) program, the initiative will provide access to cutting-edge technologies and support universities in building a diverse semiconductor workforce.

The first program, launching in 2025, will concentrate on training students, educators, and military service members transitioning to civilian careers to expand participation in the chip design sector.

Synopsys has expanded its hardware-assisted verification (HAV) portfolio with new HAPS-200 prototyping and ZeBu-200 emulation systems, powered by AMD Versal Premium VP1902 adaptive SoC. The new systems offer significant improvements in performance and capabilities:

The HAPS-200 prototyping system delivers industry-leading runtime performance with 4X improved debug performance over HAPS-100, supporting up to 10.8 billion gates. The ZeBu-200 emulation system provides up to 2X higher runtime performance compared to its predecessor, with capacity up to 15.4 billion gates.

The systems are built on Synopsys EP-Ready Hardware platform, allowing flexible configuration between emulation and prototyping use-cases. ZeBu Server 5 now scales beyond 60 billion gates for complex SoC and multi-die designs. The company's hybrid technology with Synopsys Virtualizer now supports multi-threading, enabling Android boot in under 10 minutes.