Welcome to our dedicated page for Synopsys news (Ticker: SNPS), a resource for investors and traders seeking the latest updates and insights on Synopsys stock.
Synopsys Inc. reports developments across electronic design automation, semiconductor intellectual property, silicon design, simulation and analysis solutions, and design services. Company news commonly covers AI-powered design flows, hardware-assisted verification, interface IP, multiphysics simulation, digital twin capabilities, and engineering software that supports chip, system, and product development.
Recurring updates also include customer and ecosystem work with semiconductor foundries, processor and GPU platforms, cloud infrastructure, aerospace programs, and other engineering users. Financial news centers on earnings releases, business outlook commentary, share repurchase activity, and the integration of Synopsys and Ansys technologies within the company’s expanded silicon-to-systems portfolio.
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Synopsys, Ansys, and Keysight Technologies announced the launch of a new 79GHz mmWave RF design reference flow for TSMC's 16nm FinFET technology, enhancing the development of integrated circuits (ICs) for autonomous systems. This reference flow is pivotal for applications requiring high reliability, including automotive radar and 5G connectivity. The collaboration aims to deliver optimal performance, security, and reliability, tackling challenges in RF design. Key elements include Synopsys Custom Design Family, Ansys's multiphysics signoff analysis, and Keysight's electromagnetic simulation tools, which together enhance the sensitivity and reliability of autonomous systems. The new design reference flow promises to push the boundaries of RF and mmWave technology, aligning with growing demands in next-gen autonomous applications.
Synopsys has partnered with TSMC to enhance the design of next-generation system-on-chips (SoCs) using TSMC's advanced N2 process. This collaboration offers significant improvements, including a 15% speed boost or 30% power reduction compared to the N3E process, along with increased chip density. This development enables designers to accelerate their time to market and optimize their SoC designs. TSMC's head of Design Infrastructure Management highlighted the success of their partnership in meeting stringent design targets across various applications, including AI and high-performance computing. With an established track record in 3nm technology, Synopsys's certified EDA and IP solutions are set to streamline the transition to N2 process designs.
Synopsys (Nasdaq: SNPS) has enhanced its collaboration with TSMC and Ansys to optimize multi-die systems for advanced technologies, including 7nm, 5nm, and 3nm processes. This partnership aims to address challenges in power, thermal integrity, and reliability associated with multi-die system designs. Key highlights include the integration of Synopsys' EDA and IP solutions with TSMC's 3DFabric™ technologies, enabling efficient die/package co-design and comprehensive system validation. The collaboration also showcases the successful tape-out of the Universal Chiplet Interconnect Express (UCIe) PHY IP on TSMC's N3E process, establishing a standard for low-latency die-to-die connectivity. Synopsys continues to lead in providing robust solutions for semiconductor design and manufacturing.