Synopsys Inc. reports developments across electronic design automation, semiconductor intellectual property, silicon design, simulation and analysis solutions, and design services. Company news commonly covers AI-powered design flows, hardware-assisted verification, interface IP, multiphysics simulation, digital twin capabilities, and engineering software that supports chip, system, and product development.
Recurring updates also include customer and ecosystem work with semiconductor foundries, processor and GPU platforms, cloud infrastructure, aerospace programs, and other engineering users. Financial news centers on earnings releases, business outlook commentary, share repurchase activity, and the integration of Synopsys and Ansys technologies within the company’s expanded silicon-to-systems portfolio.
Synopsys (SNPS) has entered into an accelerated share repurchase agreement with JPMorgan Chase Bank to repurchase $1 billion of stock. Synopsys will receive approximately 1,735,000 shares initially, with the remainder, if any, settled on or before January 5, 2027. The final share count will depend on average daily volume-weighted share prices during the repurchase period, less a discount.
Synopsys (SNPS) outlined its growth strategy and financial targets, expecting fiscal 2027 revenue growth of approximately 15% year over year. Revenue guidance is $11.1 billion–$11.2 billion for the year ending October 31, 2027. The company targets GAAP earnings per share of $8.16–$8.61 and operating margin of approximately 20.7%; adjusted targets are $19.04–$19.12 and approximately 44.0%, respectively.
Synopsys targets approximately 15% annual revenue growth from fiscal 2026 through fiscal 2030, with adjusted operating margin reaching approximately 50%. Fiscal 2027 free cash flow, operating cash flow less capital spending, is targeted at approximately $3.1 billion. It intends to repurchase approximately $1 billion in shares over the coming months, subject to market conditions. Multiple customers have committed to application-optimized chip-design IP, including Amazon. A preferred-partner collaboration with OpenAI will develop GPT-Synopsys for chip design.
Synopsys (SNPS) and OpenAI signed a multi-year agreement to jointly develop GPT-Synopsys, a specialized AI model for semiconductor design. OpenAI will license Synopsys' electronic design automation (EDA) tools, which support chip-design workflows. The partnership includes a revenue-sharing arrangement and joint research and go-to-market work to make the model available worldwide.
Early technology engagements with semiconductor customers are underway. The planned service will bundle computing resources, the model and tool licenses, run on OpenAI-hosted infrastructure, and integrate with Synopsys.ai and Synopsys Autopilot. Customer design data will not be used to train the model.
Synopsys (SNPS) announced a multi-year agreement worth more than $1 billion with Amazon to expand its custom-chip engineering collaboration. Amazon is the lead customer for Synopsys' expansion into application-optimized silicon IP, reusable chip-design technology tailored to specific applications. The business is evolving to a license-plus-royalty model intended to deliver value as production volumes grow.
The agreement expands Amazon's use of Synopsys' chip-design, simulation and AI tools. The companies plan to optimize Synopsys software on Trainium and Graviton and develop custom AI capabilities for engineering workflows. Synopsys is also adopting Amazon EC2, cloud storage and Bedrock to accelerate its own product development.
Synopsys (SNPS) introduced AgentEngineer solutions and its Autopilot platform for autonomous engineering across silicon-to-systems design workflows.
The agents cover verification, system validation, implementation, analog, manufacturing, and simulation and analysis. The platform offers workflow orchestration and customer choice of models, tools and infrastructure. Demonstrated results include up to 50x faster verification closure, 20% higher coverage, a 30% productivity boost and 2x better token efficiency. Fujitsu reported a 10–30% productivity boost in RTL code generation using Verification AgentEngineer capabilities. More than 50 engagements are underway; Synopsys plans general availability by the end of 2026.
Synopsys (SNPS) and TSMC announced expanded collaboration to accelerate next-generation AI, high-performance computing, and advanced semiconductor system design using TSMC's latest process and packaging technologies.
The companies introduced certified EDA flows for TSMC A14 across digital and analog design, including agentic AI capabilities for implementation-to-signoff convergence. Synopsys is adding AI-assisted workflows via Custom Compiler and Fusion Compiler, and new agentic AI chiplet floorplan co-optimization on the Synopsys 3DIC Compiler platform supporting TSMC 3DFabric. The partnership also advances multi-die IVR co-design on CoWoS, co-packaged optics design on TSMC COUPE technology, and an expanded 2nm-focused, silicon-proven IP portfolio spanning PCIe 7.0, HBM4, LPDDR6/5X/5, 224G Ethernet, UCIe, OTP, SLM PVT monitoring, and additional IP on N3P, N2P and compact “C” nodes from 6nm to 3nm.
Synopsys (Nasdaq: SNPS) reported third quarter fiscal 2026 revenue of $2.477 billion, up from $1.740 billion a year earlier, with broad-based strength led by Design Automation and contributions from Ansys. GAAP net income from continuing operations was $545.8 million, or $2.84 per diluted share, versus $1.50 in the prior-year quarter. Non-GAAP net income was $752.5 million, or $3.91 per diluted share, up from $3.39.
The company reported a third quarter non-GAAP operating margin of 41.6%, compared with a GAAP operating margin of 14.4%, reflecting adjustments for amortization of acquired intangibles, stock-based compensation, restructuring and acquisition/divestiture items. Synopsys raised its full-year 2026 outlook, targeting revenue of $9.690–$9.740 billion and non-GAAP EPS of $15.04–$15.10, with an expected non-GAAP operating margin of about 41.5% and operating cash flow of approximately $2.8 billion.
Synopsys (Nasdaq: SNPS) announced expanded collaborations with Intel Foundry, certifying its AI-powered EDA implementation and signoff flows and integrated multiphysics analysis for the Intel 14A process. The collaboration extends design enablement from design technology co-optimization (DTCO) to system-aware co-design across silicon, package, IP, and system domains.
Synopsys is also broadening its interface and foundation IP portfolio, already available for Intel 18A and 18A-P, to support Intel 14A. New IP for Intel 14A includes 224G SerDes, PCIe 7.0, USB 4, eUSB, embedded memories, logic libraries, and IOs to help reduce integration risk and accelerate time-to-tapeout for AI and multi-die designs.
Synopsys (NASDAQ: SNPS) introduced new autonomous agentic AI workflows for chip design, developed with Microsoft and available for evaluation on Microsoft Discovery. According to Synopsys, the fully-autonomous debug closure workflow, powered by AgentEngineer technology, has shown 25–40% reductions in debug cycle time, cutting weeks of engineering effort.
A second autonomous implementation and closure workflow, using Synopsys implementation agents and Fusion Compiler on Azure, has demonstrated improved quality-of-results. AMD is actively evaluating these workflows for next-generation products. Synopsys is showcasing the solutions at the 2026 DAC Chips to Systems Conference, where customers can see demonstrations and request evaluation access.
Synopsys (NASDAQ: SNPS) announced at the 2026 DAC Chips to Systems Conference new fully autonomous, long-running AI agents for chip and electronics-system engineering, developed in collaboration with NVIDIA. The agentic workflows span EDA and CAE, using NVIDIA Nemotron and CUDA-X on NVIDIA’s accelerated computing platform secured by OpenShell.
Key offerings include a fully autonomous design verification workflow that orchestrates the full chip verification lifecycle, delivering up to 50X faster time-to-validated RTL and 20% higher coverage, autonomous AMS workflows with up to 3X productivity gains, and a GPU-accelerated portfolio of 20+ EDA and multiphysics products, such as PrimeSim SPICE with up to 18X speedup. Customers are evaluating these capabilities, with broader availability planned for the second half of 2026.