Synopsys and Intel Foundry Fast-Track Customer Readiness from Silicon to Systems on Intel 14A

Q: What multi-die and packaging capabilities does Synopsys support for Intel Foundry customers?

Synopsys supports multi-die design using its 3DIC Compiler with Intel EMIB and EMIB-T packaging. According to Synopsys, the reference flow includes early bump and TSV planning, automated UCIe and HBM routing, and unified multiphysics analysis across dies, interconnect, and package.

Rhea-AI Impact

(Neutral)

Rhea-AI Sentiment

(Positive)

Rhea-AI Summary

Synopsys (Nasdaq: SNPS) announced expanded collaborations with Intel Foundry, certifying its AI-powered EDA implementation and signoff flows and integrated multiphysics analysis for the Intel 14A process. The collaboration extends design enablement from design technology co-optimization (DTCO) to system-aware co-design across silicon, package, IP, and system domains.

Synopsys is also broadening its interface and foundation IP portfolio, already available for Intel 18A and 18A-P, to support Intel 14A. New IP for Intel 14A includes 224G SerDes, PCIe 7.0, USB 4, eUSB, embedded memories, logic libraries, and IOs to help reduce integration risk and accelerate time-to-tapeout for AI and multi-die designs.

News Explained

Synopsys expands Intel 14A design enablement, adding certified flows and multi-die packaging support while 14A IP availability remains unstated.

Synopsys announced expanded collaboration with Intel Foundry and certification of AI-powered implementation and signoff flows for Intel 14A; the immediate structural change is added design-enablement capability for customers.

Its 3DIC Compiler reference design flow supports Intel EMIB and EMIB-T packaging, including bump and TSV planning, UCIe and HBM routing, and unified multiphysics analysis across dies, interconnects, and package.

The release distinguishes IP available today for Intel 18A and Intel 18A-P from the expansion to Intel 14A, so it does not establish that the newly listed 14A IP titles are already available today.

Market Context

Historical event 1071980 recorded a 2.98% 24-hour move after a related Synopsys product announcement...

Analysis

Historical event 1071980 recorded a 2.98% 24-hour move after a related Synopsys product announcement. That record adds context to this collaboration; current insider sentiment is Net Selling, while risk data categorizes short positioning as low.

Key Figures

Intel process technology: 14A Intel process technologies: 18A and 18A-P SerDes interface: 224G SerDes +2 more

5 metrics

Intel process technology 14A EDA flow certification and IP support

Intel process technologies 18A and 18A-P Existing certified flows and IP portfolio

SerDes interface 224G SerDes Interface IP optimized for Intel 14A

PCIe interface PCIe 7.0 Interface IP optimized for Intel 14A

USB interface USB 4 Interface IP optimized for Intel 14A

Historical Context

5 past events · Latest: Jul 22 (Neutral)

Pattern 5 events

Date	Event	Sentiment	24h Move	Catalyst
Jul 22	Earnings date notice	Neutral	-1.1%	Scheduled third-quarter fiscal 2026 results and investor-day dates were announced.
Jun 17	Product availability	Positive	+3.0%	Multiphysics Fusion solutions became available for customer deployment with reported runtime improvements.
Jun 15	Partnership announcement	Positive	-1.3%	Murata simulation models became accessible through Synopsys electromagnetic and thermal analysis tools.
May 28	Foundry collaboration	Positive	-8.6%	Samsung Foundry collaboration introduced AI-powered flows and certified interface IP for advanced processes.
May 27	Board appointment	Positive	-8.6%	Jesse Cohn joined the board under a cooperation agreement with Elliott Investment Management.

24h Move is the share-price change in the day after each event; other market factors may also have contributed.

Pattern Detected

Positive collaboration and AI-related announcements in the supplied history produced mixed outcomes, including reactions of +2.98%, -1.32%, and -8.61%.

Key Terms

design technology co-optimization, serdes, ucie

3 terms

design technology co-optimization technical

"advancing design enablement from design technology co-optimization (DTCO)"

Design technology co-optimization is the process of jointly adjusting a product’s design (how a chip is laid out) and the manufacturing steps (how the chip is made) so both work together for the best results. For investors it matters because tighter coordination can reduce production costs, improve performance and yields, and speed time-to-market—like tailoring a suit while choosing the fabric so it fits perfectly and wastes less material.

serdes technical

"Interface IP, including 224G SerDes, PCIe 7.0, USB 4 and eUSB"

SerDes (short for serializer/deserializer) is an electronic function that converts parallel streams of data into a single fast serial stream and then converts it back, like packing many lanes of traffic into one high-speed highway and unpacking them at the other end. Investors care because SerDes chips and blocks determine how quickly and efficiently devices, data centers and networks can move information; improvements or bottlenecks affect product performance, production costs, and demand across the semiconductor and communications supply chain.

ucie technical

"automated UCIe and HBM routing"

UCIe (Universal Chiplet Interconnect Express) is an industry standard for connecting small processor or memory building blocks, called chiplets, inside a single package so they work together like parts of a single chip. For investors, it matters because it can lower manufacturing costs, speed product development, and enable more flexible, high-performance semiconductors—similar to using interchangeable Lego pieces instead of carving one large block—potentially affecting makers’ competitiveness and profit margins.

AI-generated analysis. How Rhea-AI works. Not financial advice.

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07/27/2026 - 09:00 AM

Certified AI-powered EDA flows, integrated multiphysics analysis, and broad IP portfolio accelerate Angstrom-scale AI and multi-die designs

Key Highlights

Certified AI-powered EDA flows and multiphysics analysis for Intel 14A designs: Provide early insight into power integrity, thermal, and electromagnetic effects, improving predictability and accelerating convergence
From DTCO to system-aware co-optimization: Extends co-optimization across silicon, package, IP and system domains to enable full system realization with optimal PPA
Multi-die and advanced packaging leadership: Synopsys 3DIC Compiler platform extends exploration-to-signoff support to designs integrated with Intel EMIB and Intel EMIB-T, enabling multi-die designs
Broad IP portfolio for faster time-to-tapeout: Interface and Foundation IP for Intel 14A — including PCIe 7.0, 224G SerDes, USB 4 and eUSB reduce integration risk and accelerate design readiness

SUNNYVALE, Calif., July 27, 2026 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced at the 2026 DAC Chips to Systems Conference, expanded collaborations with Intel Foundry with the certification of AI-powered EDA flows on Intel 14A process technology, advancing design enablement from design technology co-optimization (DTCO) to system-aware co-design, building on its certified and production-ready EDA flows and IP portfolio for Intel 18A and Intel 18A-P technologies. As AI and high-performance computing designs move beyond monolithic scaling, success requires connecting process technology with AI-powered EDA flows, multi-die design, integrated multiphysics analysis, and broad IP portfolio to accelerate system-level realization.

"Angstrom-scale design is no longer only about extracting more power, performance, and area from a process node. It is about turning process innovation into predictable system-level outcomes," said Michael Buehler-Garcia, Senior Vice President at Synopsys. "Together with Intel Foundry, Synopsys is helping customers accelerate convergence, reduce late-stage rework, and achieve first-pass silicon success. We applaud the Intel Foundry team for their progress on Intel 14A to expand the capabilities of advanced semiconductor manufacturing."

"In this increasingly AI-driven world, Intel Foundry is committed to supporting our customers by accelerating innovation and providing predictable execution from silicon to packaging on our most advanced technologies," said Shawn Han, SVP and GM, Foundry Services, Intel Corporation. "Our wide-ranging collaboration with Synopsys, including AI-driven, certified flows and IP, gives our customers greater ease of use and confidence to achieve their design goals."

System-Aware Co-Design: EDA Meets Multiphysics

At angstrom-scale geometries with backside power delivery and dense 3D integration, electrical, thermal, and mechanical effects can no longer be effectively analyzed in isolation. Synopsys is uniquely positioned to address this challenge with the integration of Synopsys certified, AI-powered implementation and signoff flows and multiphysics analysis — including power integrity, thermal, and electromagnetic solutions on Intel 14A.

Enabling the Multi-Die Era

With multi-die design now mainstream in AI and HPC, Synopsys and Intel Foundry are extending their proven collaboration to enable efficient system-level integration, analysis, and optimization of advanced chiplet-based architectures. The Synopsys reference design flow based on 3DIC Compiler supports Intel Embedded Multi-die Interconnect Bridge (EMIB) and Embedded Multi-die Interconnect Bridge-T (EMIB-T) advanced packaging technology, with early bump and TSV planning, automated UCIe and HBM routing, and unified multiphysics analysis across dies. Designers can analyze and optimize power delivery networks, thermal gradients, and signal integrity concurrently across die, Intel EMIB and EMIB-T interconnect, and package, catching system-level issues at design time rather than after tapeout.

Advancing Ecosystem Readiness with Broad IP Portfolio Across Intel 18A, Intel 18A-P and Intel 14A

Synopsys and Intel Foundry continue to enable AI and HPC innovation with Synopsys' expanding portfolio of high-performance interface and foundation IP available today for Intel 18A and Intel 18A-P while expanding to support Intel 14A technologies, helping reduce integration risk and accelerate time-to-tapeout for complex SoCs and multi-die designs. New titles optimized for Intel 14A include:

Interface IP, including 224G SerDes, PCIe 7.0, USB 4 and eUSB, addresses the high throughput and connectivity demands of next-generation AI and HPC applications
Foundation IP, including embedded memories, logic libraries, and IOs, helps optimize performance, power, and area while lowering total cost of ownership.

Resources

Blog: Learn more about Process Design Kits and how Synopsys and Intel Foundry Are Accelerating Customer Success
Blog: Learn about the Next-Generation EMIB-T Packaging: A Collaboration Between Synopsys and Intel Foundry
Webinar: Learn about EMIB Design Methodology using Synopsys Tools

Join Synopsys at the 2026 DAC Chips to Systems Conference

Attendees can visit the Synopsys' booth #631 for demonstrations of the latest solutions and collaborations. For a complete list of Synopsys sessions and activities at DAC 2026, visit the Synopsys DAC 2026 event page.

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. Learn more at www.synopsys.com.

© 2026 Synopsys, Inc. All rights reserved. Synopsys, Ansys, the Synopsys and Ansys logos, and other Synopsys trademarks are available at https://www.synopsys.com/company/legal/trademarks-brands.html. Other company or product names may be trademarks of their respective owners.

Forward-Looking Statements

This press release contains forward-looking statements, which involve risks, uncertainties and other factors that could cause our actual results, time frames, or achievements to differ materially. Information on potential risks, uncertainties and other factors that could affect our results is included in filings we make with the SEC from time to time, including in the sections entitled "Risk Factors" in our latest Annual Report on Form 10-K and Quarterly Report on Form 10-Q.

Contacts

Kelli Wheeler: kelliw@synopsys.com
Pete Smith: pete.smith@synopsys.com 
corp-pr@synopsys.com

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SOURCE Synopsys, Inc.

FAQ

What did Synopsys (SNPS) announce about Intel 14A at DAC 2026?

Synopsys announced certified AI-powered EDA flows and multiphysics analysis support for Intel 14A. According to Synopsys, this extends design enablement from DTCO to system-aware co-design, linking silicon, packaging, IP, and system domains for advanced AI and multi-die designs.

How does the Synopsys and Intel Foundry collaboration on Intel 14A benefit AI and HPC designs?

The collaboration enables AI-powered implementation, signoff flows, and multiphysics analysis on Intel 14A. According to Synopsys, designers gain early insight into power integrity, thermal, and electromagnetic effects, improving predictability, accelerating convergence, and supporting angstrom-scale AI and high-performance computing systems.

What multi-die and packaging capabilities does Synopsys support for Intel Foundry customers?

Synopsys supports multi-die design using its 3DIC Compiler with Intel EMIB and EMIB-T packaging. According to Synopsys, the reference flow includes early bump and TSV planning, automated UCIe and HBM routing, and unified multiphysics analysis across dies, interconnect, and package.

Which Synopsys IP is available or expanding for Intel 18A, 18A-P, and 14A technologies?

Synopsys offers high-performance interface and foundation IP for Intel 18A and 18A-P and is expanding to Intel 14A. According to Synopsys, new Intel 14A titles include 224G SerDes, PCIe 7.0, USB 4, eUSB, embedded memories, logic libraries, and IOs.

How does Synopsys’ multiphysics analysis on Intel 14A improve system-aware co-design?

Synopsys integrates AI-powered flows with power integrity, thermal, and electromagnetic analysis on Intel 14A. According to Synopsys, this addresses angstrom-scale challenges where electrical, thermal, and mechanical effects must be analyzed together, helping catch system-level issues during design instead of after tapeout.

What does system-aware co-design mean in the Synopsys and Intel Foundry partnership?

System-aware co-design links process, EDA tools, packaging, and IP to optimize full systems. According to Synopsys, the Intel Foundry collaboration extends beyond DTCO, enabling co-optimization across silicon, package, IP, and system domains for predictable system-level outcomes on Intel 14A and 18A nodes.