Welcome to our dedicated page for Synopsys news (Ticker: SNPS), a resource for investors and traders seeking the latest updates and insights on Synopsys stock.
Synopsys Inc. reports developments across electronic design automation, semiconductor intellectual property, silicon design, simulation and analysis solutions, and design services. Company news commonly covers AI-powered design flows, hardware-assisted verification, interface IP, multiphysics simulation, digital twin capabilities, and engineering software that supports chip, system, and product development.
Recurring updates also include customer and ecosystem work with semiconductor foundries, processor and GPU platforms, cloud infrastructure, aerospace programs, and other engineering users. Financial news centers on earnings releases, business outlook commentary, share repurchase activity, and the integration of Synopsys and Ansys technologies within the company’s expanded silicon-to-systems portfolio.
Synopsys (Nasdaq: SNPS) announced the expansion of its Technology Alliance Partner (TAP) program at the RSA Conference, showcasing integrations between its Intelligent Orchestration solution and tools from partners like CloudBees and GitHub Actions. The TAP program simplifies integration of application security solutions for over 40 DevOps vendors, allowing automated security controls within existing toolchains. Recognized by Gartner and Forrester, Synopsys aims to enhance application security while maintaining development velocity through these partnerships.
Synopsys, Inc. (Nasdaq: SNPS) announced that CFO Trac Pham will present at the 49th Annual J.P. Morgan Global Technology, Media and Communications Conference on May 25, 2021, at 2:10 p.m. ET. The presentation can be accessed via live webcast through the Synopsys corporate website. A replay will be available one hour after the event and will remain accessible for 30 days. Synopsys is a leader in electronic design automation and offers a comprehensive portfolio for software applications and semiconductor development.
Synopsys, Inc. (Nasdaq: SNPS) announced transformative advancements in emulation technology with the introduction of the ZeBu EP1, the first 10 MHz emulation solution, and ZeBu Empower, a power-aware emulation system. These innovations boost performance in hardware and software verification for complex system-on-chips (SoCs) across various sectors including HPC, 5G, AI, and automotive. The enhancements include a significant emulation throughput gain and tools designed for multi-billion gate designs, underscoring Synopsys' leadership in verification hardware.
Synopsys, Inc. (Nasdaq: SNPS) announced that Xsight Labs has adopted its ZeBu® Server 4 emulation solution for the validation of the X1 intelligent networking switch processor. The ZeBu Server 4 offers 7 billion gate cloud capacity, enhancing Xsight Labs' pre-tapeout validation processes. With the ability to run extensive networking tests, the solution facilitates full system software driver development. The ZeBu platform is noted for its speed, offering 2X performance compared to competitors, while consuming significantly less power.
Synopsys, Inc. (Nasdaq: SNPS) will release its second quarter fiscal year 2021 results on May 19, 2021, after market close. A conference call is scheduled for 2:00 p.m. PT (5:00 p.m. ET) featuring Aart de Geus and Trac Pham.
Financial information will be available on their website prior to the call. A live webcast is also accessible, with replays available starting at 4:00 p.m. PT on the same day until the announcement of third quarter results in August 2021.
Synopsys, Inc. (Nasdaq: SNPS) announced that Nanya Technology has adopted the Synopsys Custom Design Platform to enhance its memory design capabilities. This transition from incumbent tools aims to streamline Nanya's design flow and improve productivity in high-growth sectors including mobile and automotive applications. Nanya reports multiple successful memory design tapeouts using Synopsys solutions, which promise faster results compared to legacy systems. Synopsys continues to expand its influence in semiconductor design, reflecting a growing trend among companies to utilize its advanced EDA solutions.
On May 4, 2021, Synopsys (Nasdaq: SNPS) announced the completion of its acquisition of MorethanIP, enhancing its DesignWare® Ethernet Controller IP portfolio. This acquisition introduces Ethernet Digital Controller IP capable of supporting data rates from 10G to 800G, including MAC and PCS for 200G/400G and 800G Ethernet. The deal strengthens Synopsys' low-latency, high-performance solutions for networking, AI, and cloud computing SoCs. Although financial terms were not disclosed, the acquisition adds a skilled R&D team with extensive industry experience.
Synopsys (Nasdaq: SNPS) will unveil its new Intelligent Orchestration application security automation solution during the RSA Conference on May 17-20, 2021. This solution enhances security testing within development workflows to improve speed and efficiency. By intelligently determining the necessary security tests based on application changes and risk policies, it optimizes security without overwhelming developers. Key benefits include seamless pipeline integration, risk-based testing, and automated reporting, aimed at addressing challenges faced by organizations integrating security into DevOps.
Synopsys, Inc. (Nasdaq: SNPS) has announced the expansion of its Software Integrity Group's partner program, led by new vice president Tom Herrmann. This initiative aims to enhance customer access to application security products by growing its global channel partner network. The company expects to double partner revenue in 2021 while restructuring operations for further growth in 2022. Herrmann's leadership, alongside successful initial partner relationships, positions Synopsys for accelerated growth, focusing on profitability and ease of collaboration for partners.
Synopsys (Nasdaq: SNPS) announced the deployment of its Fusion Compiler by Arm, enhancing power, performance, and area (PPA) for Arm Neoverse V1 and N2 cores. The Fusion Compiler utilizes a unique single data model and hyper-converged optimization to facilitate quick design closure and bring-up for system-on-chip (SoC) applications in data centers, high-performance computing, 5G, and AI. This collaboration promises improved architecture for hyperscale computing and cloud workloads, ensuring faster design processes and optimized results.