Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies

Rhea-AI Summary

Synopsys and Intel Foundry have announced a major collaboration on angstrom-scale chip designs for Intel 18A and 18A-P technologies. The partnership features production-ready EDA flows and the industry's broadest IP portfolio, optimized for Intel's advanced process nodes.

Key developments include:

• Production-ready digital and analog EDA flows for Intel 18A and 18A-P technologies
• Early design technology co-optimization for Intel 14A-E
• Enhanced multi-die design capabilities through Intel's EMIB-T packaging technology
• Broad IP portfolio supporting 224G Ethernet, PCIe 7.0, UCIe, USB4, and other technologies

Synopsys has joined the Intel Foundry Accelerator Design Services Alliance and the new Intel Foundry Accelerator Chiplet Alliance, strengthening their ecosystem partnership. The collaboration aims to accelerate the development of high-performance AI and HPC chip designs, leveraging Intel's PowerVia backside power delivery and RibbonFET Gate-all-around transistor architecture.

Positive

• Production-ready EDA flows for Intel's latest 18A and 18A-P nodes, enabling faster market entry for customers
• Broadest IP portfolio development for Intel 18A, including critical components like 224G Ethernet and PCIe 7.0
• Strategic membership in Intel Foundry Accelerator Design Services Alliance and Chiplet Alliance, strengthening market position
• Early access to Intel's 14A-E node development, maintaining competitive advantage
• Expansion into multi-die design solutions with Intel's EMIB-T technology, opening new revenue streams

Negative

• None.

Synopsys Production-Ready EDA Flows and Broadest IP Portfolio Deliver Leading PPA for Intel Foundry's Advanced Processes and Packaging Technologies

Highlights

• Production-ready Synopsys digital and analog EDA flows for Intel 18A and Intel 18A-P technologies pave the way for broad adoption and accelerate development of high-performance designs; engaged in early design technology co-optimization for Intel 14A-E
• Optimized EDA reference flow with a unified exploration-to-signoff platform accelerates 2.5D/3D multi-die designs for Intel's EMIB-T advanced packaging technology
• Broadest portfolio of high-performance and low-power IP for Intel 18A and expanded Synopsys IP support for Intel 18A-P offers customers faster time-to-tapeout
• Announcing membership in Intel Foundry Accelerator Design Services Alliance and the new Intel Foundry Accelerator Chiplet Alliance to advance Intel Foundry adoption and innovation

SUNNYVALE, Calif., April 29, 2025 /PRNewswire/ -- At today's Intel Foundry Direct Connect 2025 event, Synopsys, Inc. (Nasdaq: SNPS) announced broad EDA and IP collaborations with Intel Foundry, including availability of its certified AI-driven digital and analog design flows for the Intel 18A process node and production-ready EDA flows for the Intel 18A-P process node with RibbonFET Gate-all-around transistor architecture and the industry's first commercial foundry implementation of PowerVia backside power delivery.  

To drive multi-die design innovation forward, Synopsys and Intel Foundry are collaborating to enable Intel's new Embedded Multi-die Interconnect Bridge-T (EMIB-T) advanced packaging technology with an EDA reference flow powered by Synopsys 3DIC Compiler.

With its EDA flows, multi-die solution, and broad portfolio of Synopsys' foundation and interface IP on Intel 18A and Intel 18A-P, Synopsys is helping designers accelerate the development of highly optimized AI and HPC chip designs from silicon to systems.

In a keynote presentation at today's event, John Koeter, Senior Vice President, for the Synopsys IP Group, emphasized: "The successful collaboration between Synopsys and Intel Foundry is advancing the semiconductor industry with silicon to system design solutions to meet the evolving needs for AI and high-performance computing applications. Our production-ready EDA flows, IP, and multi-die solution, provides our mutual customers with comprehensive technologies to accelerate the development of chip designs that meet or exceed their requirements."

"Our continued collaboration with Synopsys enables engineering teams to accelerate 'systems of chips' innovation utilizing our unique systems foundry capabilities and optimized Synopsys EDA flows and IP on Intel 18A and Intel 18A-P process nodes to create differentiated designs with faster time-to-results," said Suk Lee, VP & GM of Ecosystem Technology Office, Intel Foundry. "Together, Intel Foundry and Synopsys are furthering design, manufacturing, and packaging co-optimization so our customers can meet the demands of the AI era."

Advancing Design Innovation with Comprehensive EDA and Multi-Die Solutions 
Synopsys' digital and analog design flows are certified for Intel 18A process node and production-ready for Intel 18A-P enabling faster delivery of advanced-node SoCs with higher quality-of-results. Synopsys IP and EDA flows are also optimized for power and area on the Intel 18A and Intel 18A-P process nodes to take advantage of Intel's PowerVia backside power delivery network enabling thermal-aware implementation for PowerVia based designs. RibbonFET-driven synthesis and optimization enable designers to achieve differentiated power, performance, and area (PPA) on Intel 18A and Intel 18A-P process nodes. This is a result of an extensive design technology co-optimization (DTCO) effort between Intel Foundry and Synopsys engineering teams.

Synopsys and Intel Foundry are now engaging in early design technology co-optimization for Intel 14A-E to establish the readiness of Synopsys EDA flows for the next generation advanced node.

Synopsys and Intel have extended their collaboration to help mutual customers realize the PPA advantages of multi-die designs by enabling Intel's EMIB-T advanced packaging technology with Synopsys' 3DIC Compiler. EMIB-T combines the benefits of EMIB 2.5D and Foveros 3D packaging technologies for high interconnect densities at die sizes beyond the reticle limit. The EMIB-T reference flow is powered by Synopsys' unified exploration-to-signoff platform, allowing efficient EMIB-T designs with early bump and TSV planning and optimization, and automated UCIe and HBM routing for high quality-of-results and fast 3D heterogeneous integration. Synopsys 3DIC Compiler allows feasibility and partitioning, prototyping and floorplanning, and multiphysics signoff in a single environment, allowing efficient design creation, implementation, optimization, and closure. 

Synopsys Expands IP Portfolio for Advanced Angstrom-Level Designs
The introduction of angstrom-level processes will be crucial for next-generation AI and HPC chips, delivering optimized performance, power, area, and latency. To accelerate time-to-market for these designs, Synopsys is developing the industry's broadest IP portfolio for Interface, Foundation, and SLM (Silicon Lifecycle Management) IP on Intel 18A process node, including 224G Ethernet, PCIe 7.0, UCIe, USB4, embedded memories, logic libraries, IOs, and PVT sensors. Utilizing Intel's PowerVia backside power delivery technology, Synopsys IP will enhance power distribution and performance, enabling advanced and differentiated chip designs with Intel Foundry technologies.

Further Strengthening Intel Foundry Ecosystem to Accelerate Adoption and Innovation 
Synopsys is further expanding its collaboration with Intel Foundry and the ecosystem by joining the Intel Foundry Accelerator Design Services Alliance and the new Intel Foundry Accelerator Chiplet Alliance. As a member of the latest Intel Foundry Alliance, Synopsys commits to offering its design services, in addition to optimized EDA tools and IP, to help customers accelerate their advanced chip designs. As a founding member of the new Intel Foundry Chiplet Alliance, Synopsys will further enable interoperability, manufacturability and design solutions supporting multi-die chips on Intel 18A.

Additional Resources
Synopsys is exhibiting and speaking at Intel Foundry Direct Connect today at the San Jose McEnery Convention Center, Booth #35. For more information, visit the Synopsys Intel Foundry Direct Connect event page.

About Synopsys
Catalyzing the era of pervasive intelligence, Synopsys, Inc. (Nasdaq: SNPS) delivers trusted and comprehensive silicon to systems design solutions, from electronic design automation to silicon IP and system verification and validation. We partner closely with semiconductor and systems customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.  Learn more at www.synopsys.com.

© 2025 Synopsys, Inc. All rights reserved. Synopsys, the Synopsys logo, and other Synopsys trademarks are available at https://www.synopsys.com/company/legal/trademarks-brands.html. Other company or product names may be trademarks of their respective owners. 

Editorial Contact
Kelli Wheeler 
Synopsys, Inc.
corp-pr@synopsys.com 

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SOURCE Synopsys, Inc.

FAQ

What is the Intel 18A collaboration with Synopsys (SNPS) announced in April 2025?

Synopsys announced production-ready EDA flows and IP portfolio for Intel's 18A and 18A-P process nodes, featuring RibbonFET architecture and PowerVia backside power delivery. The collaboration aims to accelerate development of AI and HPC chip designs.

How will Synopsys (SNPS) support Intel's EMIB-T packaging technology?

Synopsys is enabling Intel's EMIB-T advanced packaging through its 3DIC Compiler, offering unified exploration-to-signoff platform for efficient 2.5D/3D multi-die designs with automated UCIe and HBM routing capabilities.

What IP portfolio is Synopsys (SNPS) developing for Intel 18A process?

Synopsys is developing the industry's broadest IP portfolio for Intel 18A, including 224G Ethernet, PCIe 7.0, UCIe, USB4, embedded memories, logic libraries, IOs, and PVT sensors, optimized with PowerVia technology.

Which Intel Foundry alliances did Synopsys (SNPS) join in 2025?

Synopsys joined two key Intel Foundry alliances: the Accelerator Design Services Alliance and the Chiplet Alliance, offering design services, EDA tools, and IP to support advanced chip designs and multi-die solutions.

What are the key benefits of Synopsys (SNPS) EDA flows for Intel 18A-P?

Synopsys' EDA flows for Intel 18A-P enable faster delivery of advanced-node SoCs with better quality results, optimized power and area performance, and thermal-aware implementation using PowerVia technology.