Synopsys Collaborates with TSMC to Drive the Next Wave of AI and Multi-Die Innovation
Synopsys (NASDAQ:SNPS) has announced an expanded collaboration with TSMC to advance AI and multi-die innovation through enhanced EDA and IP solutions. The partnership focuses on certified digital and analog flows for TSMC's N2P and A16 processes using TSMC NanoFlex architecture.
Key developments include the 3DIC Compiler platform for 3D stacking and CoWoS packaging, AI-optimized photonic flow for TSMC-COUPE technology, and the industry's broadest IP portfolio optimized for TSMC's N2/N2P processes. The collaboration has already enabled multiple customer tape-outs and supports various high-performance standards including HBM4, 1.6T Ethernet, and PCIe 7.0.
Synopsys (NASDAQ:SNPS) ha annunciato un'espansione della collaborazione con TSMC per avanzare l'innovazione AI e multi-die attraverso soluzioni EDA e IP potenziate. La partnership si concentra su flussi digitali e analogici certificati per i processi N2P e A16 di TSMC utilizzando l'architettura NanoFlex di TSMC.
Gli sviluppi chiave includono la piattaforma 3DIC Compiler per impilaggio 3D e confezionamento CoWoS, flusso fotonico ottimizzato AI per la tecnologia TSMC-COUPE, e il portfolio IP più ampio del settore ottimizzato per i processi N2/N2P di TSMC. La collaborazione ha già permesso molte tape-out di clienti e supporta vari standard ad alte prestazioni tra cui HBM4, 1.6T Ethernet e PCIe 7.0.
Synopsys (NASDAQ:SNPS) ha anunciado una colaboración ampliada con TSMC para avanzar en IA e innovación multi-die mediante soluciones EDA e IP mejoradas. La asociación se centra en flujos digitales y analógicos certificados para los procesos N2P y A16 de TSMC, utilizando la arquitectura NanoFlex de TSMC.
Los desarrollos clave incluyen la plataforma Compilador 3DIC para apilamiento 3D y encapsulado CoWoS, flujo fotónico optimizado para IA para la tecnología TSMC-COUPE, y la cartera de IP más amplia de la industria optimizada para los procesos N2/N2P de TSMC. La colaboración ya ha permitido varias tape-outs de clientes y soporta diversos estándares de alto rendimiento, entre los que destacan HBM4, 1.6T Ethernet y PCIe 7.0.
Synopsys (NASDAQ:SNPS)가 확장된 협업을 TSMC와 발표하여 향상된 EDA 및 IP 솔루션을 통해 AI 및 다이-다이 혁신을 추진합니다. 파트너십은 인증된 디지털 및 아날로그 흐름에 초점을 두고 TSMC의 N2P 및 A16 공정과 TSMC NanoFlex 아키텍처를 사용합니다.
주요 개발로는 3D 적층 및 CoWoS 패키징을 위한 3DIC Compiler 플랫폼, TSMC-COUPE 기술용 AI 최적화 포토닉 흐름, 그리고 N2/N2P 공정용으로 최적화된 업계에서 가장 넓은 IP 포트폴리오가 있습니다. 이 협력은 이미 다수의 고객 테이프아웃을 가능하게 했으며 HBM4, 1.6T Ethernet, PCIe 7.0 등 고성능 표준을 지원합니다.
Synopsys (NASDAQ:SNPS) a annoncé une collaboration élargie avec TSMC pour faire avancer l'IA et l'innovation multi-die grâce à des solutions EDA et IP améliorées. Le partenariat se concentre sur des flux numériques et analogiques certifiés pour les procédés N2P et A16 de TSMC en utilisant l'architecture NanoFlex de TSMC.
Les développements clés incluent la plateforme 3DIC Compiler pour l'empilement 3D et l'emballage CoWoS, le flux photonique optimisé IA pour la technologie TSMC-COUPE, et le portefeuille IP le plus vaste de l’industrie optimisé pour les procédés N2/N2P de TSMC. La collaboration a déjà permis plusieurs tape-outs clients et prend en charge divers standards haute performance, dont HBM4, 1.6T Ethernet et PCIe 7.0.
Synopsys (NASDAQ:SNPS) hat eine erweiterte Zusammenarbeit mit TSMC angekündigt, um KI- und Multi-Die-Innovation durch verbesserte EDA- und IP-Lösungen voranzutreiben. Die Partnerschaft konzentriert sich auf zertifizierte digitale und analoge Flows für TSMCs N2P- und A16-Prozesse unter Verwendung der NanoFlex-Architektur von TSMC.
Zu den Schlüsselerungen gehören die 3DIC Compiler-Plattform für 3D-Staplung und CoWoS-Verpackung, der AI-optimierte Photonik-Flow für die TSMC-COUPE-Technologie und das branchenweit umfassendste IP-Portfolio, das für TSMCs N2/N2P-Prozesse optimiert ist. Die Zusammenarbeit hat bereits mehrere Kunden-Tape-Outs ermöglicht und unterstützt verschiedene Hochleistungsstandards, darunter HBM4, 1.6T Ethernet und PCIe 7.0.
شركة سينوبسيس (ناسداك: SNPS) أعلنت توسيع التعاون مع TSMC لدفع ابتكار AI وتعدد الرقاقات من خلال حلول EDA و IP المحسّنة. تركز الشراكة على تدفقات رقمية وتناظرية معتمدة لعمليات N2P و A16 من TSMC باستخدام بنية NanoFlex من TSMC.
تشمل التطورات الرئيسية منصة مُولِّف 3DIC لعملية التكديس الثلاثي وعبور CoWoS، و تدفق فوتوني محسّن AI لتقنية TSMC-COUPE، وأوسع محفظة IP في الصناعة مُحسّنة لعمليات N2/N2P من TSMC. لقد مكنت الشراكة بالفعل عدة tape-outs للعملاء وتدعم معايير أداء عالٍ متعددة بما في ذلك HBM4 و 1.6T Ethernet و PCIe 7.0.
Synopsys 宣布与 TSMC 扩大合作，通过增强的 EDA 和 IP 解决方案推进 AI 与多芯片（multi-die）创新。该伙伴关系聚焦于 TSMC 的 N2P 与 A16 工艺的 认证数字和模拟流，采用 TSMC 的 NanoFlex 架构。
关键进展包括用于 3D 堆叠和 CoWoS 封装的 3DIC Compiler 平台，用于 TSMC-COUPE 技术的 AI 优化光子流，以及业界最广的 IP 产品组合，针对 TSMC 的 N2/N2P 工艺进行了优化。该合作已实现多家客户的 tape-out，并支持包括 HBM4、1.6T Ethernet、PCIe 7.0 等多项高性能标准。
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Insights
Synopsys strengthens TSMC partnership for advanced AI chip design, reinforcing leadership in EDA and IP for next-generation semiconductor technology.
This collaboration between Synopsys and TSMC represents a significant advancement in semiconductor design capabilities, particularly for AI and multi-die chip architectures. The certification of Synopsys' digital and analog flows on TSMC's N2P and A16 processes using TSMC NanoFlex architecture demonstrates Synopsys' continued commitment to supporting the industry's most advanced nodes. This is critical as these next-generation processes enable significant improvements in chip performance and power efficiency.
The 3DIC Compiler platform is particularly noteworthy as it addresses one of the semiconductor industry's most challenging frontiers: multi-die integration. The successful customer tape-outs mentioned validate that Synopsys' tools can effectively handle complex 3D stacking and CoWoS (Chip-on-Wafer-on-Substrate) technologies. This is essential for overcoming the physical limitations of traditional semiconductor scaling.
Equally important is Synopsys' comprehensive IP portfolio optimized for TSMC's processes. By offering IP that supports advanced standards like HBM4, 1.6T Ethernet, UCIe, and PCIe 7.0, Synopsys is enabling customers to integrate cutting-edge connectivity into their designs without developing these complex components from scratch. The emphasis on automotive-specific IP for N5A and N3A processes also positions Synopsys well in the rapidly growing market for advanced automotive semiconductors.
The collaboration on silicon photonics for TSMC-COUPE technology is particularly forward-looking, as photonic ICs represent a potential breakthrough for data-intensive applications where traditional electronic interconnects become bottlenecks. The AI-optimized photonic flow addresses critical multi-wavelength and thermal requirements that are essential for reliable operation of these advanced systems.
This partnership reinforces Synopsys' position as a critical enabler in the semiconductor ecosystem, particularly as the industry increasingly focuses on specialized AI chips and complex heterogeneous integration. By helping customers navigate the complexities of advanced nodes and multi-die designs, Synopsys is cementing its role in the next wave of semiconductor innovation.
Synopsys' EDA tools and IP for TSMC's advanced processes position it as a crucial enabler for next-generation AI hardware development.
This partnership between Synopsys and TSMC is particularly significant for the AI hardware landscape. The certified tools and IP portfolio directly address the most pressing challenges in advanced AI chip design today. Modern AI accelerators are increasingly moving toward multi-die architectures to overcome the physical limitations of monolithic designs, and Synopsys' 3DIC Compiler platform provides the critical capabilities needed to implement these complex systems.
The mention of multiple customer tape-outs using advanced 3D stacking and CoWoS packaging technologies is especially important. This indicates that Synopsys' tools aren't just theoretical solutions but are enabling practical implementations of next-generation AI hardware designs. The semiconductor industry is facing growing challenges with traditional scaling, making 3D integration increasingly essential for continued performance improvements in AI chips.
Synopsys' support for TSMC's N2P process is strategically important for AI hardware designers. This process represents one of the most advanced nodes available, providing significant density, performance, and power efficiency improvements critical for next-generation AI accelerators. The A16 process support further expands options for designers seeking optimal performance/power tradeoffs.
The AI-optimized photonic flow for TSMC-COUPE technology addresses a crucial emerging area in AI hardware design. As AI models grow larger and distributed training/inference becomes more common, the interconnect between chips and systems becomes a critical bottleneck. Silicon photonics offers promising solutions to these bandwidth challenges, potentially enabling significantly faster chip-to-chip communication with lower power consumption.
Synopsys' comprehensive IP portfolio, including support for standards like HBM4 (high-bandwidth memory) and UCIe (Universal Chiplet Interconnect Express), provides essential building blocks for AI system designers. HBM4 addresses the memory bandwidth requirements of data-hungry AI accelerators, while UCIe enables standardized connections between different chiplets in heterogeneous multi-die designs – a key architecture for many advanced AI systems.
AI-Driven EDA and Broad IP Solutions Enable Differentiated Designs on TSMC Advanced Processes and SoIC Technologies
Key Highlights
- Certified digital and analog flows on the TSMC N2P and A16™ processes using TSMC NanoFlex™ architecture boost performance and speed analog design migration
- 3DIC Compiler platform and 3D-enabled IP enable multiple customer tape outs using advanced 3D stacking and CoWoS packaging technologies
- AI-optimized photonic flow for TSMC Compact Universal Photonic Engine (TSMC-COUPE™) technology enhances system design performance and addresses multi-wavelength and thermal requirements
- Industry's broadest IP portfolio, on TSMC N2/N2P, optimized for low power, speeds path to silicon success and reduces integration risk
Building on Synopsys' continued collaboration with TSMC is the availability of certified digital and analog flows, along with the enabled Synopsys.ai™ on TSMC's N2P and A16™ processes using TSMC NanoFlex™ architecture. In addition, Synopsys provides robust automotive IP solutions for TSMC N5A and N3A processes and best-in-class Interface and Foundation IP solutions, delivering highest level of safety, security and reliability while enabling maximum performance with the lowest power for advanced chips.
"Our close collaboration with TSMC continues to empower engineering teams to achieve successful tape outs on the industry's most advanced packaging and process technologies," said Michael Buehler-Garcia, Senior Vice President at Synopsys. "With certified digital and analog EDA flows, 3DIC Compiler platform, and our comprehensive IP portfolio optimized for TSMC's advanced technologies, Synopsys is enabling mutual customers to deliver differentiated multi-die and AI designs with enhanced performance, lower power, and accelerated time to market."
"TSMC has been working closely with our long-standing Open Innovation Platform® (OIP) ecosystem partners like Synopsys to help customers achieve high quality-of-results and faster time-to-market for leading-edge SoC designs," said Aveek Sarkar, Director of the Ecosystem and Alliance Management Division at TSMC. "With the ever-growing need for energy efficient and high-performance AI chips, the OIP ecosystem collaboration is crucial for providing our mutual customers with certified EDA tools, flows and high-quality IP to meet or exceed their design targets."
Synopsys EDA Flows Deliver Enhanced Performance on TSMC Advanced Processes
Synopsys' analog and digital flows, along with the enabled Synopsys.ai, are certified on TSMC N2P and A16™ processes using TSMC NanoFlex™ architecture to help optimize performance, power, and to scale chip designs to advanced semiconductor technologies. Certified capabilities for designs on TSMC A16™ Super Power Rail (SPR) process improve power distribution and system performance, while maintaining thermal robustness of backside routing designs. Synopsys' pattern-based pin access methodology has been enhanced for TSMC A16™ node to deliver competitive area results. In addition, Synopsys is collaborating with TSMC on the design flow development for TSMC's A14 process and its first process design kit release scheduled for the later part of 2025.
Synopsys IC Validator™ signoff physical verification solution is certified for TSMC A16™ process to support DRC and LVS checking. IC Validator's high-capacity elastic architecture seamlessly scales PERC rules to handle TSMC's N2P full-path electrostatic discharge (ESD) verification with improved turnaround time.
Advanced 3D Stacking and CoWoS Technologies Demonstrate Successful 3D Integration
Synopsys' 3DIC Compiler's unified exploration-to-signoff platform has been enabled to support the TSMC-SoIC® (SoIC-X) technology, including 3D stacked designs and silicon interposer and bridge with CoWoS® technologies, resulting in several customer tape outs. With 3DIC Compiler, customers can achieve higher productivity and faster turnaround times with the platform's automated UCIe and HBM routing, TSV and bump planning, and multi-die signoff verification.
In addition, the ongoing collaboration between Synopsys and TSMC on silicon photonics has enabled an AI-optimized photonic IC flow for TSMC-COUPE™ technology to deliver enhanced system performance and address multi-wavelength and thermal requirements in multi-die and AI designs.
Synopsys Industry-Leading IP Portfolio Paves the Way for Silicon Success
Synopsys is accelerating semiconductor innovation on next-generation TSMC's N2P/N2X processes with the industry's most comprehensive portfolio of best-in-class Foundation and Interface IP. The Synopsys IP portfolio enables the latest high-performance standards, including HBM4, 1.6T Ethernet, UCIe, PCIe 7.0, and UALink, as well as a robust roadmap for automotive, IoT, and HPC applications. Synopsys provides a comprehensive suite of high-performance proven PHYs, embedded memories, high-density logic libraries, programmable IO, and NVM IP. With dedicated IP for N5A and N3A automotive nodes, along with advanced SRAM and Foundation IP for 5nm and 3nm SoCs, Synopsys empowers customers to meet the demanding requirements of next-generation designs across a broad range of markets.
Additional Resources
- Mutual customers of TSMC and Synopsys will be speaking about their experience with these new offerings to attendees of TSMC's OIP Forums. For information as to the topics and the joint presenters, please visit TSMC's OIP North America web page.
- Learn about how Synopsys collaborates with TSMC to enable multiphysics and photonics design solutions here.
- Synopsys is also hosting several demonstrations at Booth #204. For more information, visit Synopsys TSMC OIP North America page.
- Additional information on IP for 3D Multi-Die Designs is available here.
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. Learn more at www.synopsys.com.
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FAQ
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