Synopsys Introduces Software-Defined Hardware-Assisted Verification to Enable AI Proliferation

Synopsys (Nasdaq: SNPS) announced software-defined hardware-assisted verification (HAV) enhancements on March 11, 2026, delivering up to 2x performance and 2x capacity for ZeBu Server 5 and new HAPS-200 and ZeBu-200 12 FPGA platforms.

Rhea-AI Summary

Synopsys (Nasdaq: SNPS) announced software-defined hardware-assisted verification (HAV) enhancements on March 11, 2026, delivering up to 2x performance and 2x capacity for ZeBu Server 5 and new HAPS-200 and ZeBu-200 12 FPGA platforms. New industry-first hardware-assisted test-automation and Real-Number Models enable earlier detection of cache-coherency and subsystem bugs and faster software bring-up across data center to edge AI designs. The HAPS-200 12 FPGA and HAPS-200 1 FPGA are available today; ZeBu-200 12 FPGA is available in Q3 2026. Continuous software updates and EP-Ready Hardware aim to extend system lifetime value and enable emulation-to-prototyping configurability.

Positive

• Up to 2x performance boost for ZeBu Server 5 via software-defined updates
• 2x capacity for HAPS-200 and ZeBu-200 12 FPGA platforms versus prior 6 FPGA systems
• Industry-first hardware-assisted test automation for earlier detection of cache-coherency and subsystem bugs
• HAPS-200 1 FPGA desktop platform available today for IP verification and software bring-up
• EP-Ready Hardware enables configurability between prototyping and emulation to extend reuse

Negative

• ZeBu-200 12 FPGA platform availability is scheduled for Q3 2026, creating staggered delivery across product line

Argus Mar 11 session

+0.08% close to close Open Argus

Details

News Market Reaction – SNPS

On Mar 11, the day this news came out, SNPS closed 0.08% above the previous close.

Data tracked by StockTitan Argus for the Mar 11 session.

Key Figures

ZeBu Server 5 performance: up to 2x boost HAV capacity scale: up to 2x capacity HAPS & ZeBu capacity: 2x higher capacity +5 more

ZeBu Server 5 performance

up to 2x boost

Software-defined approach for hardware-assisted verification

HAV capacity scale

up to 2x capacity

Modular hardware-assisted verification for AI-era mega designs

HAPS & ZeBu capacity

2x higher capacity

New HAPS-200 12 FPGA and ZeBu-200 12 FPGA vs prior 6 FPGA platforms

LLM growth cadence

double every four months

Growth rate cited for large language model size

Interface data rate trend

2x every three years

Interface data rates trend driving verification complexity

Verification workload scale

quadrillions of cycles

Required verification cycles for AI chip designs

Converge 2026 dates

March 11-12, 2026

Synopsys Converge event timing referenced in the release

ZeBu-200 12 availability

Q3 2026

Availability timing for new ZeBu-200 12 FPGA platform

Previous AI Reports

5 past events · Latest: Jan 06

Same Type 5 events

1. Jan 06

   AI automotive showcase

   24h Move

   +3.0%

   Showcased AI-driven, software-defined automotive engineering efficiencies at CES 2026.

2. Oct 28

   AI & NVIDIA GTC

   24h Move

   -1.8%

   Highlighted Agentic AI and GPU-accelerated simulation at NVIDIA GTC Washington, D.C.

3. Oct 08

   AI simulation adoption

   24h Move

   +2.4%

   Showcased Ansys SimAI platform usage for >10x faster automotive simulations.

4. Sep 03

   EDA AI expansion

   24h Move

   +0.0%

   Expanded Synopsys.ai Copilot capabilities, boosting design speed and engineer productivity.

5. Jul 29

   Ansys AI release

   24h Move

   +7.3%

   Ansys 2025 R2 introduced broad AI-powered simulation enhancements and tools.

24h Move is the share-price change in the day after each event; other market factors may also have contributed.

Key Terms

hardware-assisted verification, fpga, emulation, prototyping, +4 more

8 terms

hardware-assisted verification technical

"announced advancements across its leading hardware-assisted verification (HAV) portfolio"

Hardware-assisted verification uses a dedicated physical component — such as a secure chip or trusted module — to check identities, measurements or transactions instead of relying only on software. Like a bank vault with a built-in fingerprint reader, it makes authentication and tamper-detection harder to fake, which can reduce fraud, regulatory risk and downtime. Investors watch it because strong hardware-based security can protect revenue, lower liability and create a competitive edge in products and services.

fpga technical

"The new HAPS-200 12 FPGA and ZeBu-200 12 FPGA systems address the complexity"

A field-programmable gate array (FPGA) is a type of computer chip whose internal wiring can be changed after it is made, allowing engineers to program custom hardware functions without designing a new chip. For investors, FPGAs matter because that flexibility lets companies quickly adapt products to new software, standards, or customer needs—like a toolbox that can be rearranged to build different machines—so demand and pricing can shift with trends in data centers, telecommunications, AI, and specialized electronics.

emulation technical

"extends emulation and prototyping capacity by 2x and delivers leading performance"

Emulation is the act of copying or imitating how a product, system, or process behaves so that one thing can stand in for another—like running old video game software on a new console that pretends to be the old one. For investors, emulation matters because it can speed product development, expand market access, or lower costs by reusing proven behavior, but it can also signal competitive risk, regulatory scrutiny, or potential legal challenges tied to intellectual property or safety standards.

prototyping technical

"extends emulation and prototyping capacity by 2x and delivers leading performance"

A prototype is an early, working version of a product or process built to test how an idea performs in the real world, like a draft model or dress rehearsal. For investors, successful prototyping shows that a concept can be made to work, helps estimate development costs and timelines, and reduces technical and market risk before large-scale manufacturing or regulatory approval are pursued.

cache‑coherency technical

"earlier detection of cache‑coherency and subsystem‑level bugs for maximum coverage"

Cache-coherency is the system-level guarantee that when multiple fast local memories hold copies of the same data, any change made in one place is quickly reflected everywhere so everyone reads the most up-to-date value. Think of it like a shared document where edits on one person’s copy automatically appear on all others so no one works from an old version. For investors, coherency affects product speed, power use, reliability and scalability in multi-core processors and distributed devices, which in turn influences competitiveness, customer satisfaction and development costs.

real-number models (rnm) technical

"Real-Number Models (RNM) emulation enables fast, scalable abstraction of analog behavior"

Real-number models are mathematical tools that represent prices, rates, and other financial quantities as continuous numbers rather than categories or simple counts. Think of them like a dimmer switch instead of an on/off light: they let analysts track small, smooth changes and calculate precise forecasts, valuations, and risk measures. Investors use these models because their outputs feed pricing, trading and risk decisions, though results depend on the model’s assumptions about how smoothly markets move.

fault emulation technical

"new fault emulation capabilities enable scalable fault injection and analysis"

Fault emulation is the deliberate simulation of errors or breakdowns in a product, system, or process to see how it behaves and whether safeguards work. For investors, it matters because this kind of testing reveals hidden risks, helps prevent costly failures or recalls, and demonstrates that a company’s products, manufacturing, or software are robust and compliant — like running a fire drill to find weak spots before a real emergency hits.

ip verification technical

"ideal for IP verification and software bring-up using Synopsys Interface Prototyping Kits"

IP verification is the process of checking that a company actually owns, controls, or has the legal right to use specific intellectual property such as patents, trademarks, copyrights, or proprietary technology. For investors, verified IP is like confirming clear property deeds: it reduces the risk that a competitor can claim ownership, protects potential revenue streams from products or licensing, and supports a company's competitive edge and valuation.

AI-generated analysis. How Rhea-AI works. Not financial advice.

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New product capabilities deliver leading performance, capacity, and industry-first hardware-assisted test-automation capabilities to accelerate AI silicon innovation from data center to edge

Key Highlights

• Software-defined approach enables an up to 2x performance boost for ZeBu Server 5 and scales capacity up to 2x with modular HAV for AI-era mega designs
• New HAPS-200 12 FPGA and ZeBu-200 12 FPGA platforms for mainstream designs feature EP‑Ready Hardware that extends emulation and prototyping capacity by 2x and delivers leading performance for emulation and prototyping use cases 
• New, industry-first hardware-assisted test automation capabilities enable faster, earlier detection of cache‑coherency and subsystem‑level bugs for maximum coverage

SUNNYVALE, Calif., March 11, 2026 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced advancements across its leading hardware-assisted verification (HAV) portfolio, including new hardware platforms and capabilities to support the ever-expanding demand for AI chip verification from the data center to the edge. Synopsys HAV platforms, powered by the company's unique software-defined capabilities, set new performance, scalability, and use case benchmarks for verifying the world's most sophisticated multi-die and AI chips amidst compounding design complexity and time-to-market requirements.

AI chip verification complexity is escalating rapidly as large language models continue to double in size roughly every four months, and interface data rates advance at a 2x rate every three years. Simultaneously, edge AI architectures are driving aggressive throughput, latency, and power‑efficiency targets that further expand the design and validation workload. To keep pace, the industry requires HAV solutions to support broader application coverage and run quadrillions of verification cycles, enabling first‑time‑right silicon and a seamless ability to integrate heterogeneous AI systems.

"As AI-driven systems become more complex, verification must scale just as quickly. Hardware-assisted verification is no longer optional. It is critical to meeting aggressive time-to-market goals and ensuring silicon readiness," said Salil Raje, Senior Vice President and General Manager, Adaptive and Embedded Computing Group, AMD. "FPGA-based emulation and prototyping play a central role in that effort by accelerating system bring-up and enabling earlier software development. Our collaboration with Synopsys reflects that focus. Through joint optimization of Synopsys ZeBu with the AMD Vivado™ software stack, and by leveraging AMD EPYC™ processors for compute acceleration, we are reducing compile times and helping customers move to accurate system models faster."

"As AI becomes more pervasive across almost every industry and products are now workload-optimized and silicon-powered, building high confidence early that the workloads are running to spec on the silicon under development is critical," said Ravi Subramanian, Chief Product Management Officer at Synopsys. "Our software-defined, hardware-assisted verification solutions deliver continuous innovation. They are a powerful force multiplier to scale verification productivity and meet the growing demand for pre-silicon development across industries."

The latest advancements across Synopsys' software-defined hardware-assisted verification portfolio, include:

Breakthrough performance and capacity for the AI era: The latest software-defined updates and modular HAV are available across the ZeBu and HAPS platforms. Of note, with these updates, the industry's highest capacity-scalable emulation platform, ZeBu Server 5, supports complex designs to meet the demands of mega designs supporting data center AI training and inference, GPU, custom accelerators, and networking IPU/DPU workloads. Modular HAV for HAPS enables the largest prototypes for software development, with further improvements for compute, storage, and bring-up capabilities.

New HAPS and ZeBu platforms: The new HAPS-200 12 FPGA and ZeBu-200 12 FPGA systems address the complexity and high-performance requirements for data center-sub-system, mobile, client, server, consumer, and edge AI applications. They deliver 2x higher capacity compared to previous 6 FPGA platforms utilizing the flagship AMD Versal™ Premium VP1902 adaptive SoCs, offering EP-Ready Hardware-enabled configurability between prototyping and emulation. Synopsys also introduces the new HAPS-200 1 FPGA platform as a desktop system ideal for IP verification and software bring-up using Synopsys Interface Prototyping Kits.

"As NVIDIA's AI platforms have become software‑defined to meet rising performance and scalability demands, verification must evolve in the same way," said Narendra Konda, Vice President, Hardware Engineering at NVIDIA. "Synopsys' software‑defined hardware‑assisted verification and the new HAPS‑200 12 FPGA systems are accelerating our system‑level verification and validation, helping us deliver complex AI platforms on aggressive schedules. And, Synopsys modular hardware-assisted verification enables deeper collaboration across our ecosystem."

Software-defined HAV capabilities extend system lifetime value: Continuous software improvements deliver compounding performance gains, increased debug productivity, as well as additional use case capabilities for both new and installed systems. The Synopsys HAV portfolio supports new, industry-first Hardware-Assisted Test Solutions, test automation capabilities that allow teams to stress corner cases for processor, memory, and I/O subsystems as well as full-system coherency validation and observe system behavior under realistic workloads in emulation long before silicon is ready. For mixed-signal and system-level designs, Real-Number Models (RNM) emulation enables fast, scalable abstraction of analog behavior within digital-centric verification flows for faster software bring-up. For safety-critical and high-reliability designs, new fault emulation capabilities enable scalable fault injection and analysis across RTL simulation, emulation, and prototyping.

"Verifying hardware for our highly anticipated rack-scale AMD Helios solution – marked by massive AI scale, complex subsystems, and robust software stacks – demands scalable and versatile verification platforms," said Alex Starr, Corporate Fellow, AMD. "The Synopsys software-defined, HAV capabilities with EP-Ready Hardware are critical to how we perform CPU, GPU, and AI subsystems verification as well as full-system validation. Teams can also cover an expanded number of use cases in the pre-silicon phase, encompassing analog, digital, and software design verification using Real-Number Models (RNM) in emulation. As well, the flexibility to reconfigure and reuse hardware across projects and move seamlessly between emulation and prototyping as AI designs grow in both physical size and software stack volume are essential to delivering the high-performance, interoperable AI infrastructure at scale needed to meet the world's growing AI demands."

Availability & Additional Resources
Software-defined enhancements are being rolled out continuously across the HAV portfolio, with the new capabilities available to users today. The new EP‑Ready HAPS-200 12 FPGA and ZeBu-200 12 FPGA platforms are available today and in Q3 2026, respectively. HAPS-200 1 FPGA platform is available today.

• Product Page: Synopsys HAV Solutions Family   
• Blog: Introducing Software-Defined Hardware-Assisted Verification: A New Benchmark for AI-Era Chip Design 
• Video: Software-Defined Hardware-Assisted Verification for the AI Era

Follow Synopsys Converge 2026 News and Updates 
Synopsys Converge is taking place March 11-12, 2026, at the Santa Clara Convention Center. Follow news and updates as well as keynote details and replays via the Synopsys Converge Newsroom, on LinkedIn, and on X.

About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. Learn more at www.synopsys.com.

© 2026 Synopsys, Inc. All rights reserved. Synopsys, Ansys, the Synopsys and Ansys logos, and other Synopsys trademarks are available at https://www.synopsys.com/company/legal/trademarks-brands.html. AMD EPYC, Versal, Vivado and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other company or product names may be trademarks of their respective owners.

Contacts
Media
Kelli Wheeler: kelliw@synopsys.com
Pete Smith: pete.smith@synopsys.com
corp-pr@synopsys.com

 

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SOURCE Synopsys, Inc.

FAQ

AI-generated questions and answers. How Rhea-AI works. Not financial advice.

What performance gains did Synopsys announce for ZeBu Server 5 (SNPS) on March 11, 2026?

Synopsys said the software-defined updates can deliver up to a 2x performance boost for ZeBu Server 5. According to Synopsys, the updates also scale capacity to address mega-design AI workloads and accelerate verification cycles for large systems.

When will the new ZeBu-200 12 FPGA platform (SNPS) be available for customers?

ZeBu-200 12 FPGA is scheduled to be available in Q3 2026. According to Synopsys, HAPS-200 12 FPGA and HAPS-200 1 FPGA are available today, while ZeBu-200 follows later this year for high-capacity emulation.

How do the HAPS-200 and ZeBu-200 12 FPGA systems compare to previous 6 FPGA platforms (SNPS)?

The new 12 FPGA systems deliver 2x the capacity versus prior 6 FPGA platforms. According to Synopsys, they leverage AMD Versal Premium VP1902 and EP-Ready Hardware for better configurability between prototyping and emulation.

What is Synopsys' hardware-assisted test automation and how does it help verification (SNPS)?

Hardware-assisted test automation enables earlier, faster detection of cache-coherency and subsystem bugs in emulation. According to Synopsys, this lets teams stress corner cases and observe realistic workloads well before silicon is available.

Will Synopsys' HAV updates support mixed-signal and safety-critical designs (SNPS)?

Yes. Synopsys introduced Real-Number Models for emulating analog behavior and new fault emulation for scalable fault injection. According to Synopsys, these capabilities aid mixed-signal and safety-critical verification across RTL simulation, emulation, and prototyping.

What customers or partners are highlighted using Synopsys' software-defined HAV solutions (SNPS)?

Synopsys cites collaborations with AMD and NVIDIA to optimize ZeBu and HAPS workflows for large AI platforms. According to Synopsys, joint optimization reduces compile times and accelerates system-level verification for complex AI subsystems.