STMicroelectronics to advance next-generation chip manufacturing technology with new PLP pilot line in Tours, France
STMicroelectronics (NYSE:STM) has announced plans to develop next-generation Panel-Level Packaging (PLP) technology through a new pilot line at its Tours facility in France. The company is investing $60 million in this strategic initiative, which is expected to be operational by Q3 2026.
The advanced PLP technology represents a significant upgrade from traditional wafer-level packaging, utilizing large rectangular panels instead of circular wafers to achieve higher manufacturing throughput. ST's PLP technology, featuring Direct Copper Interconnect (DCI), currently produces over 5 million units daily on a highly automated line using 700x700mm panels.
This initiative builds upon ST's existing PLP line in Malaysia and will expand the technology's application across automotive, industrial, and consumer products, including RF, analog, power, and microcontrollers. The project will leverage synergies with the local R&D ecosystem, including the CERTEM R&D center.
STMicroelectronics (NYSE:STM) ha annunciato piani per sviluppare una tecnologia di Packaging a livello di pannello (PLP) di prossima generazione tramite una nuova linea pilota nel suo stabilimento di Tours, in Francia. L'azienda investirà 60 milioni di dollari in questa iniziativa strategica, che dovrebbe essere operativa entro il Q3 2026.
La tecnologia PLP avanzata rappresenta un significativo upgrade rispetto all'imballaggio tradizionale a livello di wafer, utilizzando grandi pannelli rettangolari invece di wafer circolari per aumentare la produttività. La tecnologia PLP di ST, con Direct Copper Interconnect (DCI), attualmente produce oltre 5 milioni di unità al giorno su una linea altamente automatizzata che utilizza pannelli da 700x700 mm.
Questa iniziativa si basa sulla linea PLP esistente in Malesia e amplierà l'applicazione della tecnologia nei settori automobilistico, industriale e di consumo, includendo RF, analogico, potenza e microcontrollori. Il progetto sfrutterà sinergie con l'ecosistema di R&D locale, incluso il centro CERTEM R&D.
STMicroelectronics (NYSE:STM) ha anunciado planes para desarrollar una tecnología de Packaging a nivel de panel (PLP) de próxima generación mediante una nueva línea piloto en su planta de Tours, Francia. La empresa invertirá 60 millones de dólares en esta iniciativa estratégica, que se espera que esté operativa para el tercer trimestre de 2026.
La tecnología PLP avanzada representa una mejora significativa respecto al empaque tradicional a nivel de wafer, utilizando paneles rectangulares grandes en lugar de obleas circulares para lograr una mayor productividad. La tecnología PLP de ST, con Direct Copper Interconnect (DCI), actualmente produce más de 5 millones de unidades diarias en una línea altamente automatizada que utiliza paneles de 700x700 mm.
Esta iniciativa se apoya en la línea PLP existente en Malasia y ampliará la aplicación de la tecnología en automotriz, industrial y de consumo, incluyendo RF, analógico, potencia y microcontroladores. El proyecto aprovechará sinergias con el ecosistema local de I+D, incluido el CERTEM R&D center.
STMicroelectronics (NYSE:STM)가 프랑스 투르에서 새로운 파일럿 라인을 통해 차세대 패널 레벨 패키징(PLP) 기술을 개발할 계획을 발표했습니다. 이 전략적 이니셔티브에 6천만 달러를 투자하며, 2026년 3분기에 가동될 예정입니다.
고급 PLP 기술은 전통적인 웨이퍼 수준 포장에 비해 큰 직사각형 패널을 사용해 원통형 웨이퍼 대신 더 높은 제조 생산량을 달성한다는 점에서 큰 업그레이드입니다. ST의 PLP 기술은 Direct Copper Interconnect (DCI)를 특징으로 하며, 현재 일일 500만 개 이상의 유닛을 700x700mm 패널을 사용하는 고도로 자동화된 라인에서 생산합니다.
이 이니셔티브는 말레이시아에 이미 존재하는 PLP 라인을 바탕으로 자동차, 산업 및 가전 제품의 RF, 아날로그, 파워, 마이크로컨트롤러를 포함한 기술 적용 범위를 확장합니다. CERTEM R&D 센터를 포함한 현지 R&D 생태계와의 시너지를 활용할 예정입니다.
STMicroelectronics (NYSE:STM) a annoncé des plans pour développer une technologie de packaging au niveau panneau (PLP) de nouvelle génération via une nouvelle ligne pilote sur son site de Tours, en France. L’entreprise investira 60 millions de dollars dans cette initiative stratégique, qui devrait être opérationnelle au 3e trimestre 2026.
La technologie PLP avancée représente une amélioration significative par rapport à l’emballage traditionnel au niveau wafer, utilisant de grands panneaux rectangulaires au lieu de wafers circulaires pour augmenter le débit de fabrication. La technologie PLP de ST, avec l’interconnexion directe en cuivre (DCI), produit actuellement plus de 5 millions d’unités par jour sur une ligne hautement automatisée utilisant des panneaux de 700x700 mm.
Cette initiative s’appuie sur la ligne PLP existante en Malaisie et étendra l’application de la technologie dans les domaines automobile, industriel et grand public, y compris RF, analogique, puissance et microcontrôleurs. Le projet tirera parti de synergies avec l’écosystème local R&D, y compris le centre CERTEM R&D.
STMicroelectronics (NYSE:STM) hat Pläne angekündigt, eine Next-Generation-Panel-Level-Packaging (PLP)-Technologie über eine neue Pilotlinie in seinem Werk Tours, Frankreich, zu entwickeln. Das Unternehmen investiert 60 Millionen Dollar in diese strategische Initiative, die voraussichtlich bis ins 3. Quartal 2026 betriebsbereit sein wird.
Die fortschrittliche PLP-Technologie stellt eine signifikante Aufrüstung gegenüber herkömmlicher Wafer-Packaging dar und verwendet große rechteckige Panels statt runder Wafer, um eine höhere Fertigungsleistung zu erreichen. STs PLP-Technologie mit Direct Copper Interconnect (DCI) produziert derzeit über 5 Millionen Einheiten pro Tag auf einer hochautomatisierten Linie mit 700x700 mm Panels.
Diese Initiative baut auf der bestehenden PLP-Linie in Malaysia auf und wird die Anwendung der Technologie in Automobil-, Industrie- und Konsumgüterbranchen erweitern, einschließlich RF, Analog, Power und Mikrokontrollern. Das Projekt wird Synergien mit dem lokalen F&E-Ökosystem nutzen, einschließlich des CERTEM F&E-Zentrums.
STMicroelectronics (NYSE:STM) أعلنت عن خطط لتطوير تقنية تعبئة على مستوى اللوحة (PLP) من الجيل التالي من خلال خط أولي جديد في منشآتها بتور بفرنسا. الشركة ستستثمر 60 مليون دولار في هذه المبادرة الاستراتيجية، والتي من المتوقع أن تكون عملية بحلول الربع الثالث من 2026.
تمثل تقنية PLP المتقدمة ترقية كبيرة مقارنة بالتعبئة التقليدية على مستوى الرقائق، حيث تُستخدم لوحات مستطيلة كبيرة بدلاً من الرقائق الدائرية لتحقيق معدل إنتاج أعلى. تقنية PLP من ST، مع ربط مباشر بالنحاس (DCI)، تنتج حالياً أكثر من 5 ملايين وحدة يومياً على خط آلي عالي باستخدام ألواح 700x700 ملم.
تُبنى هذه المبادرة على خط PLP الحالي في ماليزيا وستوسع تطبيق التكنولوجيا عبر السيارات والصناعات والمنتجات الاستهلاكية، بما في ذلك RF وanalog وPower وmicrocontrollers. سيستفيد المشروع من التآزر مع منظومة البحث والتطوير المحلية، بما في ذلك مركز CERTEM للبحوث والتطوير.
STMicroelectronics (NYSE:STM) 已宣布通过其位于法国图尔的工厂新建一条试验线，开发下一代面板级封装（PLP）技术。公司将在这一战略举措上投资6000万美元，预计将于2026年第三季度投入运行。
该先进的 PLP 技术相较传统的晶圆级封装有显著升级，使用大尺寸矩形面板替代圆形晶圆，以实现更高的制造产出。ST 的 PLP 技术采用直接铜互连（DCI），目前在一条高度自动化的生产线中，使用＜700x700mm＞面板，日产量超过500万单元。
该计划在马来西亚现有的 PLP 线基础上推进，将扩大该技术在汽车、工业和消费类产品中的应用，涵盖射频、模拟、功率和微控制器等领域。该项目将与当地的研发生态系统（包括 CERTEM 研发中心）产生协同效应。
- Investment of $60 million demonstrates commitment to advanced manufacturing capabilities
- Current PLP technology already achieving high production volumes of 5+ million units daily
- Technology enables superior performance through better power density and heat dissipation
- Expansion of manufacturing capabilities across multiple product lines (RF, analog, power, microcontrollers)
- Strategic alignment with European chip manufacturing initiatives
- Significant time gap until operational status (Q3 2026)
- Large capital investment required for implementation
- Dependent on successful integration with existing manufacturing processes
Insights
ST's $60M PLP pilot line in Tours advances critical packaging technology that will boost manufacturing efficiency and product capabilities across multiple segments.
STMicroelectronics' announcement of a new Panel-Level Packaging (PLP) pilot line in Tours represents a significant advancement in the company's manufacturing capabilities. The
The technical value of PLP technology is substantial. By replacing traditional circular wafers with larger rectangular panels, ST can process more chips simultaneously, dramatically improving manufacturing throughput. The Direct Copper Interconnect (DCI) approach they're using eliminates wire connections in favor of direct copper connections, which reduces power losses, enhances thermal performance, and enables further miniaturization.
This development is strategically important for three key reasons. First, it strengthens ST's heterogeneous integration capabilities, allowing them to combine different chip technologies more efficiently. Second, it will extend PLP technology across multiple product lines including RF, analog, power, and microcontrollers - essentially their core product portfolio. Third, it reinforces European semiconductor manufacturing capabilities, complementing their existing packaging operations in Malta.
The timing is also notable - while the pilot line won't be operational until Q3 2026, this long-term investment shows confidence in the technology's future. ST is building a multidisciplinary team combining manufacturing automation, process engineering, and data science expertise, suggesting they view advanced packaging as a critical competitive differentiator. By leveraging the local R&D ecosystem including the CERTEM center, they're creating a hub for packaging innovation that could yield advantages across their entire product range.
PR N°C3358C
STMicroelectronics to advance next-generation chip manufacturing technology with new PLP pilot line in Tours, France
- Multi-disciplinary team to further develop innovative approach to chip packaging and test manufacturing technology boosting efficiency and flexibility
- Part of ST’s strategic initiative on heterogeneous integration, contributing to technology roadmap on RF, analog, power and digital products
- Launch of the PLP pilot line in Tours supported by
$60 million investment and synergies with local R&D ecosystem
Geneva, Switzerland, September 17, 2025 -- STMicroelectronics (NYSE: STM), a global semiconductor leader serving customers across the spectrum of electronics applications, today announced new details regarding the development of the next generations of Panel-Level Packaging (PLP) technology through a pilot line in its Tours site, France, which is expected to be operational in Q3 2026.
PLP is an advanced, automated chip packaging and test process technology bringing increased manufacturing efficiency and reducing costs, and a key enabler for creating the next generation of smaller, more powerful, and cost-effective electronic devices. The large-area carrier in PLP (large rectangular shapes in place of circular wafers) enables higher manufacturing throughput, making it a more efficient solution for high-volume production. Building on its first-generation PLP line in operation in Malaysia and its global technology R&D network, ST plans to develop the next generations of its PLP technology to maintain its technological leadership and extend the use of PLP across many other ST products for automotive, industrial and consumer applications.
“The development of our PLP capabilities in our Tours site is aimed at advancing this innovative approach to chip packaging and test manufacturing technology, boosting efficiency and flexibility so it can be rolled out across a wide portfolio of applications, including RF, analog, power and microcontrollers. A multidisciplinary team of experts in manufacturing automation, process engineering, data science and analytics, as well as technology and product R&D, will collaborate on this program, which is a key part of a larger strategic initiative focused on heterogeneous integration – a scalable, efficient new approach to chip integration,” said Fabio Gualandris, President Quality, Manufacturing and Technology of STMicroelectronics. “With our fab in Malta, ST has already demonstrated its capability to deliver high-performing chip packaging and test in Europe. As we reshape our global manufacturing footprint, this new initiative in Tours will expand our process, design and manufacturing innovation capabilities supporting the development of next-generation chips in Europe”.
The development of the new PLP pilot line in Tours is supported by a capital investment of over
Technical note on PLP
For decades, the industry has relied on wafer-level packaging (WLP) and flip-chip technology to connect silicon chips to external circuitry. However, as devices become smaller and more complex, these methods have begun to reach their limits in terms of scalability and cost-effectiveness. For advanced packaging, different approaches exist or are under development; PLP is one of them.
Panel Level Packaging is a method where multiple ICs are packaged on a single, larger rectangular substrate panel, rather than on individual circular wafers. This allows for more ICs to be processed simultaneously, reducing costs and improving throughput.
ST has not only adopted PLP-DCI but has also been at the forefront of its development since 2020. The company's research and development teams have worked to prototype and scale the technology, culminating in a state-of-the-art PLP-DCI process currently in production at very high volumes of over 5 million units per day on a highly automated line using very large, 700x700mm panels.
ST’s PLP technology focuses on Direct Copper Interconnect (DCI). Direct copper interconnections replace the traditional wire connections of chips with their encapsulation support. DCI is the process by which these ICs are electrically connected to the panel substrate using copper, which is known for its excellent electrical conductivity. DCI offers superior performance compared to traditional methods that use solder bumps, which can be less reliable. This technology with direct connection without wire supports new product development by reducing power losses (such as resistance and inductance), enhancing heat dissipation and enabling miniaturization. This leads to better overall power density.
PLP-DCI also allows the integration of multiple chips within advanced packages, known as System in Package (SiP).
About STMicroelectronics
At ST, we are 50,000 creators and makers of semiconductor technologies mastering the semiconductor supply chain with state-of-the-art manufacturing facilities. An integrated device manufacturer, we work with more than 200,000 customers and thousands of partners to design and build products, solutions, and ecosystems that address their challenges and opportunities, and the need to support a more sustainable world. Our technologies enable smarter mobility, more efficient power and energy management, and the wide-scale deployment of cloud connected autonomous things. We are on track to be carbon neutral in all direct and indirect emissions (scopes 1 and 2), product transportation, business travel, and employee commuting emissions (our scope 3 focus), and to achieve our
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