Cadence Design System Inc Stock Price, News & Analysis

United Microelectronics Corporation (UMC) and Cadence Design Systems have certified the Cadence 3D-IC reference flow for UMC’s advanced chip stacking technologies. This collaboration aims to streamline the design process for edge AI, image processing, and wireless communication applications, enhancing performance while minimizing costs. The new certification supports UMC’s wafer-on-wafer stacking, demonstrating integration across various technology nodes. Cadence's Integrity 3D-IC platform will facilitate design planning, implementation, and system-level analysis, significantly accelerating the time to market for mutual customers. This partnership responds to increasing demands for 3D-IC solutions in an evolving semiconductor landscape.

Cadence Design Systems announced the certification of its Quantus FS solution by Samsung Foundry for advanced process technologies SF4, SF3E, and SF3. This certification enhances design accuracy, ensuring tighter parasitic extraction accuracy and improved capacitance and resistance verification. The Quantus FS solution is optimized for library IP characterization and is cloud-ready, enabling faster customer deployment. The collaboration aims to expedite customer adoption and improve time-to-market.

Cadence Design Systems has announced that its flagship Corporate Social Responsibility initiative, the Cadence Scholarship Program, received the CSR Times Awards 2022 in the Education category. This program aims to support underprivileged students through funding and mentorship, improving their access to professional and vocational courses. Since its inception in 2016, the program has successfully guided high school graduates toward enhanced employability, thanks to active employee participation and partnerships with NGOs such as Concern India Foundation and Joining Hands. This recognition highlights the program's impact on the education sector.

Cadence Design Systems (CDNS) announced that Global Unichip Corp. (GUC) has successfully delivered advanced high-performance computing (HPC) and CPU designs leveraging Cadence's digital solutions. Key highlights include a 3.16GHz HPC core design with a 3.5 million instance count on TSMC’s N3 process, and an 8% reduction in power and 9% area shrink in a CPU design on the N5 process using AI-enabled Cadence Cerebrus. These innovations enhance engineering productivity and demonstrate GUC's commitment to advanced chip solutions for emerging markets like AI and 5G.

Penn Electric Racing, part of the University of Pennsylvania, is enhancing its Formula Electric SAE team's performance by utilizing Cadence Celsius Thermal Solver and AWR software products for circuit validation and optimization. This initiative aims to provide students with hands-on experience in the mobility industry, contributing to their career development through teamwork and practical problem-solving. The Formula SAE competition has a history of over 40 years, equipping students to tackle real-world challenges in sustainable energy and transportation.

Cadence Design Systems, Inc. (NASDAQ: CDNS) will host its fourth quarter and fiscal year 2022 financial results webcast on February 13, 2023, at 2:00 p.m. PT. The webcast will feature Dr. Anirudh Devgan, CEO, and John Wall, CFO. Access to the recorded webcast will be available online from 5:00 p.m. PT on the same day until 5:00 p.m. PT on March 18, 2023. Cadence continues to be a leader in electronic systems design, celebrated for its workplace environment by Fortune magazine for eight consecutive years.

Cadence Design Systems has announced that its Tensilica HiFi DSP is the first digital signal processing (DSP) IP to support Dolby Atmos for cars. This innovation allows for enhanced audio experiences in automotive systems by offloading Dolby Atmos playback to a low-energy, high-performance DSP. The Tensilica HiFi DSP is widely used, licensed by 19 of the top 20 semiconductor companies, with over 1.5 billion cores shipped yearly. This partnership aims to bring superior audio clarity and immersive sound to in-car entertainment.

Cadence Design Systems has launched the first LPDDR5X memory interface IP design optimized for speeds of 8533Mbps, representing a 33% increase over previous generations. This technology is now available for customer engagements, featuring a silicon-proven PHY and high-performance controller aligned with the JEDEC JESD209-5B standard. It supports advanced applications in automotive, IoT, and networking. The architecture enhances power and performance adaptability, reinforcing Cadence's leadership in memory interface IP for future AI and automotive SoC designs.