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Cadence Design Systems develops electronic design automation software, design IP, and system design and analysis products for semiconductor and system engineering. Company updates commonly cover AI-driven chip design, certified design flows for advanced process nodes, digital twins, physics-based simulation, and computational software used from silicon design to electromechanical systems.
Recurring developments include collaborations with semiconductor, cloud and accelerated-computing partners; customer adoption of technologies such as Tensilica Vision DSP IP and Cadence ChipStack AI Super Agent; and financial results across EDA, IP, and system design and analysis. Cadence also reports on expanded simulation capabilities, including structural and multibody dynamics technologies added through the completed Hexagon design and engineering acquisition.
Cadence Design Systems (CDNS) announced that Global Unichip Corp. (GUC) has successfully delivered advanced high-performance computing (HPC) and CPU designs leveraging Cadence's digital solutions. Key highlights include a 3.16GHz HPC core design with a 3.5 million instance count on TSMC’s N3 process, and an 8% reduction in power and 9% area shrink in a CPU design on the N5 process using AI-enabled Cadence Cerebrus. These innovations enhance engineering productivity and demonstrate GUC's commitment to advanced chip solutions for emerging markets like AI and 5G.
Penn Electric Racing, part of the University of Pennsylvania, is enhancing its Formula Electric SAE team's performance by utilizing Cadence Celsius Thermal Solver and AWR software products for circuit validation and optimization. This initiative aims to provide students with hands-on experience in the mobility industry, contributing to their career development through teamwork and practical problem-solving. The Formula SAE competition has a history of over 40 years, equipping students to tackle real-world challenges in sustainable energy and transportation.
Cadence Design Systems, Inc. (NASDAQ: CDNS) will host its fourth quarter and fiscal year 2022 financial results webcast on February 13, 2023, at 2:00 p.m. PT. The webcast will feature Dr. Anirudh Devgan, CEO, and John Wall, CFO. Access to the recorded webcast will be available online from 5:00 p.m. PT on the same day until 5:00 p.m. PT on March 18, 2023. Cadence continues to be a leader in electronic systems design, celebrated for its workplace environment by Fortune magazine for eight consecutive years.
Cadence Design Systems has announced that its Tensilica HiFi DSP is the first digital signal processing (DSP) IP to support Dolby Atmos for cars. This innovation allows for enhanced audio experiences in automotive systems by offloading Dolby Atmos playback to a low-energy, high-performance DSP. The Tensilica HiFi DSP is widely used, licensed by 19 of the top 20 semiconductor companies, with over 1.5 billion cores shipped yearly. This partnership aims to bring superior audio clarity and immersive sound to in-car entertainment.
Cadence Design Systems has launched the first LPDDR5X memory interface IP design optimized for speeds of 8533Mbps, representing a 33% increase over previous generations. This technology is now available for customer engagements, featuring a silicon-proven PHY and high-performance controller aligned with the JEDEC JESD209-5B standard. It supports advanced applications in automotive, IoT, and networking. The architecture enhances power and performance adaptability, reinforcing Cadence's leadership in memory interface IP for future AI and automotive SoC designs.
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Cadence Design Systems (CDNS) and United Microelectronics Corporation (UMC) have announced successful customer adoption of their certified mmWave reference flow. Notably, Gear Radio Electronics achieved a first-pass silicon-accurate design for a low noise amplifier IC using UMC's 28HPC+ process technology and the Cadence RF solution. Their collaboration has resulted in faster turnaround times and improved design accuracy, supporting applications up to 110GHz. This initiative enhances RF design capabilities and exemplifies the effectiveness of their combined technology.
Cadence Design Systems, Inc. (Nasdaq: CDNS) will have its CEO, Anirudh Devgan, participating in a fireside chat at the Nasdaq Investor Conference in London on December 6, 2022, at 9:00 a.m. GMT. The discussion will be available live via webcast and archived for later viewing on Cadence’s website starting from 7:00 a.m. PST on December 7, 2022, until January 23, 2023. Cadence is recognized as a leader in electronic systems design, serving various industries including automotive and healthcare. For more details, visit cadence.com/cadence/investor_relations.
Cadence Design Systems (NASDAQ: CDNS) has announced that its GDDR6 IP is now silicon proven on TSMC’s N5 process technology, achieving data rates of 22Gbps, over twice that of DDR5 and 37% faster than previous versions. This advancement positions the IP for high-bandwidth memory applications in sectors such as AI/ML, 5G, and hyperscale computing. The GDDR6 IP includes both PHY and controller design, enhancing reliability and performance, thereby allowing customers to expedite development with reduced risk.
Cadence Design Systems has partnered with TSMC to enhance the N16 mmWave RF design capabilities, fostering advancements in mobile, 5G, and automotive technologies. This collaboration supports TSMC’s N16RF Design Reference Flow and process design kits, enabling efficient system-on-chip design. The full RF Design Reference Flow encompasses essential tools like passive device modeling and EM analysis, improving design robustness and productivity for mutual customers. Cadence aims to provide optimized solutions that align with evolving customer requirements.