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Cadence Design Systems develops electronic design automation software, design IP, and system design and analysis products for semiconductor and system engineering. Company updates commonly cover AI-driven chip design, certified design flows for advanced process nodes, digital twins, physics-based simulation, and computational software used from silicon design to electromechanical systems.
Recurring developments include collaborations with semiconductor, cloud and accelerated-computing partners; customer adoption of technologies such as Tensilica Vision DSP IP and Cadence ChipStack AI Super Agent; and financial results across EDA, IP, and system design and analysis. Cadence also reports on expanded simulation capabilities, including structural and multibody dynamics technologies added through the completed Hexagon design and engineering acquisition.
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Cadence Design Systems (CDNS) and United Microelectronics Corporation (UMC) have announced successful customer adoption of their certified mmWave reference flow. Notably, Gear Radio Electronics achieved a first-pass silicon-accurate design for a low noise amplifier IC using UMC's 28HPC+ process technology and the Cadence RF solution. Their collaboration has resulted in faster turnaround times and improved design accuracy, supporting applications up to 110GHz. This initiative enhances RF design capabilities and exemplifies the effectiveness of their combined technology.
Cadence Design Systems, Inc. (Nasdaq: CDNS) will have its CEO, Anirudh Devgan, participating in a fireside chat at the Nasdaq Investor Conference in London on December 6, 2022, at 9:00 a.m. GMT. The discussion will be available live via webcast and archived for later viewing on Cadence’s website starting from 7:00 a.m. PST on December 7, 2022, until January 23, 2023. Cadence is recognized as a leader in electronic systems design, serving various industries including automotive and healthcare. For more details, visit cadence.com/cadence/investor_relations.
Cadence Design Systems (NASDAQ: CDNS) has announced that its GDDR6 IP is now silicon proven on TSMC’s N5 process technology, achieving data rates of 22Gbps, over twice that of DDR5 and 37% faster than previous versions. This advancement positions the IP for high-bandwidth memory applications in sectors such as AI/ML, 5G, and hyperscale computing. The GDDR6 IP includes both PHY and controller design, enhancing reliability and performance, thereby allowing customers to expedite development with reduced risk.
Cadence Design Systems has partnered with TSMC to enhance the N16 mmWave RF design capabilities, fostering advancements in mobile, 5G, and automotive technologies. This collaboration supports TSMC’s N16RF Design Reference Flow and process design kits, enabling efficient system-on-chip design. The full RF Design Reference Flow encompasses essential tools like passive device modeling and EM analysis, improving design robustness and productivity for mutual customers. Cadence aims to provide optimized solutions that align with evolving customer requirements.
Cadence Design Systems (CDNS) announced that its Integrity 3D-IC platform is the first comprehensive solution certified for TSMC’s 3DFabric technologies. This certification facilitates advanced multi-die package design across various applications, including 5G and AI. The collaboration with TSMC includes the new 3Dblox standard, which enhances design efficiency and enables chiplet reuse. This partnership aims to expedite time-to-market for customers utilizing Cadence’s system planning and packaging capabilities, further aligning with Cadence's Intelligent System Design strategy.
Cadence Design Systems (CDNS) has partnered with TSMC to create a streamlined node-to-node migration process for analog IC blocks using TSMC's advanced technology. The collaboration allows for automated design migration, significantly improving efficiency with early customers reporting a design cycle reduction of over 2.5X. The Cadence Virtuoso design platform is central to this process, facilitating automatic schematic and layout migration while ensuring thorough optimization through simulation. This advancement supports Cadence's strategic goal of enhancing design automation and productivity.
Cadence Design Systems (CDNS) has announced certification of its digital and custom/analog design flows by TSMC for the N4P and N3E processes. This collaboration aims to enhance innovation in mobile, automotive, AI, and hyperscale computing. Customers are already utilizing these advances, achieving optimal power, performance, and area (PPA) goals while accelerating time-to-market. The enhanced capabilities include improved design methodologies and support for complex mixed-signal designs, enabled by tools like Virtuoso and Innovus.
Cadence Design Systems reported third quarter 2022 revenue of $903 million, up from $751 million in Q3 2021. Operating margin improved to 29% with net income reaching $186 million or $0.68 per diluted share. On a non-GAAP basis, operating margin was 39% and net income was $290 million or $1.06 per diluted share. For Q4 2022, expected revenue ranges from $870 million to $890 million, with GAAP EPS projected between $0.50 and $0.54. Full year revenue outlook is $3.532 billion to $3.552 billion.
Cadence Design Systems (CDNS) joins the Intel Foundry Services (IFS) U.S. Military, Aerospace and Government (USMAG) Alliance to enhance SoC designs. This collaboration aims to utilize Cadence's secure EDA tools and IP alongside Intel's manufacturing processes, benefiting mutual customers in meeting national security standards. As a member, Cadence gains access to important resources like process roadmaps and technical training. The partnership emphasizes innovation in military and aerospace applications, ensuring secure design solutions optimized for advanced process technologies.