Welcome to our dedicated page for Cadence Design System news (Ticker: CDNS), a resource for investors and traders seeking the latest updates and insights on Cadence Design System stock.
Cadence Design Systems, Inc. (Nasdaq: CDNS) is a software publisher focused on electronic design automation (EDA), design IP and system design and analysis, with a strong emphasis on AI and digital twins. The CDNS news feed highlights how the company’s computational software and Intelligent System Design™ strategy support semiconductor and systems companies across hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics.
Investors and industry followers can use this page to review company announcements on financial results, including quarterly earnings releases, backlog updates, margin disclosures and business outlooks, which Cadence distributes via press releases and related 8-K filings. These updates often include commentary from senior management and details on product and maintenance revenue, services revenue and non-GAAP metrics.
Cadence news also covers technology milestones and product introductions. Examples include LPDDR5X and LPDDR6 memory IP system solutions for AI training, inference and data center workloads, as well as announcements related to memory and interface IP for standards such as HBM, DDR5, PCIe, UCIe, UALink and high-speed Ethernet. Other releases describe the company’s Chiplet Spec-to-Packaged Parts ecosystem and Physical AI chiplet platform, developed in collaboration with partners like Arm and Samsung Foundry to support chiplet-based architectures for physical AI, data center and HPC applications.
Additional news items address strategic transactions and governance, such as the acquisition of Secure-IC, the planned acquisition of Hexagon’s design and engineering business, and board appointments including Dr. Luc Van den hove. Community-focused announcements, like the Cadence Giving Foundation’s multi-year commitment to expand the AI Hub at San José State University, provide insight into the company’s engagement with education and the broader AI ecosystem.
By following CDNS news, readers can track how Cadence’s EDA tools, design IP, AI and digital twin technologies evolve, how the company communicates its financial performance, and how strategic partnerships and acquisitions shape its role in semiconductor and system design. Bookmark this page to access an organized stream of Cadence press releases and related updates.
Cadence Design Systems (CDNS) has announced the certification of an 8nm RFIC design reference flow by Samsung Foundry, aimed at developing 5G RFICs for sub-6GHz to mmWave applications. This advanced design flow enhances productivity, electrical analysis, and design closure, enabling high-quality RFIC designs on the first pass. Key features of the flow include support for circuit simulation, electromagnetic-aware design, and post-layout extraction. This collaboration advances the design capabilities for customers in the growing 5G market, including smartphones and communications infrastructure.
Cadence Design Systems (NASDAQ: CDNS) has optimized its Voltus-XFi Custom Power Integrity solution for Samsung Foundry’s advanced 5LPE process technology. This certification enhances collaboration between the two companies, allowing customers to integrate advanced design software for creating integrated circuits (ICs) aimed at hyperscale computing, mobile, automotive, and AI applications. The Voltus-XFi solution offers a comprehensive workflow, ensuring high performance and low power consumption in line with emerging technology demands.
Cadence Design Systems has launched the Cadence Verisium Artificial Intelligence (AI)-Driven Verification Platform. This new suite uses big data and AI to enhance verification workloads, coverage, and the analysis of design bugs on complex System-on-Chips (SoCs). Built on the Cadence Joint Enterprise Data and AI (JedAI) Platform, Verisium optimizes multiple runs across SoC designs, improving productivity through advanced machine learning models. Initial apps include Verisium AutoTriage, SemanticDiff, and others, each focused on automating and streamlining the verification process.
Cadence Design Systems has launched the Cadence JedAI Platform, a significant advancement in electronic design automation (EDA) that integrates big data and AI to enhance productivity and optimize the design process. This platform unifies analytics across various Cadence applications, enabling engineers to manage both structured and unstructured data efficiently. It aims to facilitate quicker insights and improve key metrics such as power, performance, and area (PPA) across multiple designs. The platform supports cloud capabilities and is designed to meet the growing complexities in chip design across diverse industries.
Cadence Design Systems (NASDAQ: CDNS) has acquired OpenEye Scientific Software for approximately
United Microelectronics Corporation (UMC) and Cadence Design Systems (CDNS) announced the certification of Cadence's analog/mixed-signal IC design flow for UMC's 22ULP/ULL process technologies. This collaboration enhances process efficiency and shortens design cycles for applications in 5G, IoT, and displays. UMC's 22nm technology focuses on ultra-low power and leakage, providing customers with a balance of cost and performance. The certified flow includes tools like the Virtuoso design platform and Spectre AMS Designer, aimed at boosting design efficiency.
Cadence Design Systems (CDNS) has partnered with GlobalFoundries (GF) to enhance 5G mobile design through the introduction of Cadence's RF and mmWave flow for GF's 22FDX platform. This collaboration successfully designed a 28GHz 5G mmWave IC, which integrates an antenna in a system-in-package format. The design, tested by Fraunhofer IIS/EAS, exhibited strong correlation with silicon measurements. The comprehensive design flow aims to optimize performance, power efficiency, and reliability for clients.
Cadence Design Systems announces the launch of the first Verification IP (VIP) and System-Level VIP for the CXL 3.0 standard, enhancing testing and compliance in data center applications. The solution integrates with PCIe 6.0, using Cadence TripleCheck technology for effective verification. Additionally, the System VIP includes a Traffic Library for CXL and tools for performance analysis, addressing the latest CXL requirements. This release supports Cadence's broader verification flow and Intelligent System Design strategy, aiding early adopters in achieving efficient verification closure.
Cadence Design Systems (NASDAQ: CDNS) announced that Arm is utilizing its Liberate MX Trio Characterization to enhance the quality of embedded memory and speed up market delivery. This solution enabled Arm to reduce memory LVF characterization validation runtime by 7X compared to traditional Monte Carlo simulations. The automated and less error-prone process improved accuracy while minimizing manual efforts and validation time. The adoption of this characterization tool signifies Arm's commitment to meeting evolving memory characterization demands.
Cadence Design Systems will participate in the KeyBanc Technology Leadership Forum on August 9, 2022. CEO Anirudh Devgan will lead a virtual fireside chat at 7:45 a.m. MDT. The event will be webcast live, with a replay available from 7:00 a.m. PDT on August 10, 2022 until 5:00 p.m. PDT on September 16, 2022. Interested parties can access the webcast at cadence.com/cadence/investor_relations.