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Cadence Design Systems develops electronic design automation software, design IP, and system design and analysis products for semiconductor and system engineering. Company updates commonly cover AI-driven chip design, certified design flows for advanced process nodes, digital twins, physics-based simulation, and computational software used from silicon design to electromechanical systems.
Recurring developments include collaborations with semiconductor, cloud and accelerated-computing partners; customer adoption of technologies such as Tensilica Vision DSP IP and Cadence ChipStack AI Super Agent; and financial results across EDA, IP, and system design and analysis. Cadence also reports on expanded simulation capabilities, including structural and multibody dynamics technologies added through the completed Hexagon design and engineering acquisition.
Cadence Design Systems (CDNS) announced that its Integrity 3D-IC platform is the first comprehensive solution certified for TSMC’s 3DFabric technologies. This certification facilitates advanced multi-die package design across various applications, including 5G and AI. The collaboration with TSMC includes the new 3Dblox standard, which enhances design efficiency and enables chiplet reuse. This partnership aims to expedite time-to-market for customers utilizing Cadence’s system planning and packaging capabilities, further aligning with Cadence's Intelligent System Design strategy.
Cadence Design Systems (CDNS) has partnered with TSMC to create a streamlined node-to-node migration process for analog IC blocks using TSMC's advanced technology. The collaboration allows for automated design migration, significantly improving efficiency with early customers reporting a design cycle reduction of over 2.5X. The Cadence Virtuoso design platform is central to this process, facilitating automatic schematic and layout migration while ensuring thorough optimization through simulation. This advancement supports Cadence's strategic goal of enhancing design automation and productivity.
Cadence Design Systems (CDNS) has announced certification of its digital and custom/analog design flows by TSMC for the N4P and N3E processes. This collaboration aims to enhance innovation in mobile, automotive, AI, and hyperscale computing. Customers are already utilizing these advances, achieving optimal power, performance, and area (PPA) goals while accelerating time-to-market. The enhanced capabilities include improved design methodologies and support for complex mixed-signal designs, enabled by tools like Virtuoso and Innovus.
Cadence Design Systems reported third quarter 2022 revenue of $903 million, up from $751 million in Q3 2021. Operating margin improved to 29% with net income reaching $186 million or $0.68 per diluted share. On a non-GAAP basis, operating margin was 39% and net income was $290 million or $1.06 per diluted share. For Q4 2022, expected revenue ranges from $870 million to $890 million, with GAAP EPS projected between $0.50 and $0.54. Full year revenue outlook is $3.532 billion to $3.552 billion.
Cadence Design Systems (CDNS) joins the Intel Foundry Services (IFS) U.S. Military, Aerospace and Government (USMAG) Alliance to enhance SoC designs. This collaboration aims to utilize Cadence's secure EDA tools and IP alongside Intel's manufacturing processes, benefiting mutual customers in meeting national security standards. As a member, Cadence gains access to important resources like process roadmaps and technical training. The partnership emphasizes innovation in military and aerospace applications, ensuring secure design solutions optimized for advanced process technologies.
Cadence Design Systems (CDNS) has expanded its collaboration with Samsung Foundry to enhance 3D-IC design capabilities. The Cadence Integrity 3D-IC platform now supports die-on-die stacking, optimizing power, performance, and area (PPA) for complex applications. This collaboration allows users to optimize through TSV placement in stacked die designs, mitigating traditional design challenges. It streamlines the design process by enabling planning, implementation, and signoff from a single interface, aimed at improving overall productivity.
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Cadence Design Systems (CDNS) has partnered with Google Cloud to enhance semiconductor design through the Cadence Cloud Passport, offering certified cloud-ready tools. This collaboration has resulted in up to 10X improvements in design throughput and 25% performance gains on Google Cloud C2D instances versus on-premises solutions. Customers benefit from improved scalability, high-performance computing access, and reduced time-to-solution. Notably, Google silicon teams have successfully utilized Cadence tools to develop Tensor SoCs and TPUs, significantly boosting design reliability and project timelines.
Cadence Design Systems introduces the Cadence Certus Closure Solution, designed to automate the chip design closure process, reducing turnaround time from weeks to overnight. This solution features a massively parallel architecture, significantly boosting productivity by up to 10X compared to existing methodologies. The Certus Closure Solution supports essential design aspects such as 5G communications and hyperscale computing, while offering cloud readiness for extensive chip design projects. It enhances engineering productivity and integrates with existing tools for streamlined operations.
Cadence Design Systems (CDNS) will host its third quarter 2022 financial results webcast on October 24, 2022, at 2:00 p.m. Pacific Time. CEO Dr. Anirudh Devgan and CFO John Wall will participate in the event. An archived version of the webcast will be accessible from 5:00 p.m. Pacific Time on the same day until December 16, 2022. Cadence is recognized as a leader in electronic systems design, known for its Intelligent System Design strategy and has been named one of the 100 Best Companies to Work For by Fortune for eight consecutive years.