IBM Debuts World's First Sub-1 Nanometer Chip Technology

Rhea-AI Summary

IBM (NYSE:IBM) announced the world’s first sub-1 nanometer chip technology, a 0.7 nm (7 angstrom) node using a new 3D “nanostack” transistor architecture. The chip fits nearly 100 billion transistors on a fingernail-sized die, about twice the density of IBM’s 2 nm chip.

According to IBM, technical results project up to 50% higher performance or 70% better energy efficiency versus its 2 nm node, plus 40% SRAM scaling. IBM projects at least a decade of future scaling and sees a path to production in about five years.

AI-generated analysis. Not financial advice.

Positive

• First announced sub-1 nm chip technology at the 0.7 nm (7 angstrom) node
• Nearly 100 billion transistors on a fingernail-sized chip, ~2x IBM’s 2 nm density
• Projected up to 50% more performance or 70% greater energy efficiency than 2 nm
• Nanostack architecture experimentally validated with functional CMOS inverter operation
• Research shows 40% SRAM scaling, supporting high-bandwidth AI data demands
• IBM projects at least a decade of future logic scaling using nanostack

Negative

• Performance and efficiency gains are projected from research results, not yet in commercial products
• IBM sees a path to production only in about five years, delaying near-term revenue impact

News Market Reaction – IBM

-1.78%

15 alerts

-1.78% News Effect

+3.8% Peak in 8 min

-$4.48B Valuation Impact

$247.15B Market Cap

0.0x Rel. Volume

On the day this news was published, IBM declined 1.78%, reflecting a mild negative market reaction. Argus tracked a peak move of +3.8% during that session. Our momentum scanner triggered 15 alerts that day, indicating notable trading interest and price volatility. This price movement removed approximately $4.48B from the company's valuation, bringing the market cap to $247.15B at that time.

Data tracked by StockTitan Argus on the day of publication.

Key Figures

Transistor node: 0.7 nm (7 angstrom) Transistor count: 100 billion transistors Prior node comparison: 2 nm chip +5 more

8 metrics

Transistor node 0.7 nm (7 angstrom) New sub-1 nm chip technology node

Transistor count 100 billion transistors On a chip roughly the size of a fingernail

Prior node comparison 2 nm chip New chip has nearly twice the density of IBM’s 2 nm chip

Performance uplift 50 percent more performance Versus IBM’s 2 nm node chips

Energy efficiency gain 70 percent greater energy efficiency Versus IBM’s 2 nm node chips

SRAM scaling 40 percent scaling in SRAM Demonstrated in research presented at VLSI 2026

Scaling roadmap At least a decade IBM semiconductor roadmap for future scaling with nanostack architecture

Production timeline Next 5 years IBM’s expected earliest path to production for sub-1 nm nanostack technology

Peers on Argus

IBM was down about 0.8% ahead of this news, while key IT services peers showed m...

IBM was down about 0.8% ahead of this news, while key IT services peers showed mixed moves (e.g., ACN and CTSH up, FI slightly down), pointing to stock-specific rather than broad sector-driven trading.

Historical Context

5 past events · Latest: Jun 22 (Positive)

Pattern 5 events

Date	Event	Sentiment	Move	Catalyst
Jun 22	AI security partnership	Positive	+5.0%	Joined OpenAI cyber program and launched new managed application security service.
Jun 22	AI fan experience deal	Positive	-0.4%	Expanded AI-powered fan features and digital platforms for Wimbledon 2026.
Jun 17	AI risk study	Neutral	-3.1%	Released global study highlighting AI sovereignty, risk, and vendor dependency issues.
Jun 16	Apptio AI launch	Positive	+0.8%	Introduced Conversational Insights and new AI-powered spend and forecasting tools.
Jun 11	ServiceNow AI tie-up	Positive	+0.9%	Announced multi-year collaboration with ServiceNow to modernize data and IT operations using AI.

Pattern Detected

Recent IBM news has mostly seen price moves align with generally positive AI-related announcements, with only occasional divergences.

Regulatory & Risk Context

Short Interest: 3.25%

Short Interest

3.25% of float

0% 15% 30%+

low as of 2026-05-29 Days to cover: 2.27

Short positioning is relatively low, suggesting limited short-squeeze potential and a generally modest contribution to volatility from short covering.

Market Pulse Summary

This announcement highlights IBM’s sub-1 nm nanostack chip with up to 50% more performance and 70% b...

Analysis

This announcement highlights IBM’s sub-1 nm nanostack chip with up to 50% more performance and 70% better efficiency. Compared with recent AI-focused news, investors may watch how quickly IBM converts this research into production within the stated 5-year window.

Key Terms

nanostack, nanosheet, sram, high numerical aperture extreme ultraviolet

4 terms

nanostack technical

"IBM researchers developed an entirely new transistor architecture, called "nanostack,""

A nanostack is a layered combination of materials, tiny components and manufacturing steps engineered at the nanometer scale to deliver a specific function, such as sensing, targeted drug delivery or ultra‑small electronics. Think of it like the layers in a cake or the apps and settings on a smartphone that must all work together; for investors it signals how practical and costly it will be to scale, protect with patents, meet regulations and turn the underlying science into a sellable product.

nanosheet technical

"the industry's first known three-dimensional, nanosheet-based design."

A nanosheet is an ultra-thin layer of material only a few atoms thick, like a single sheet of paper compared with a ream, but made from metals, semiconductors or other compounds. Investors care because nanosheets can change how electronic components, sensors and batteries perform—enabling smaller, faster or more energy-efficient products—which can lower manufacturing costs, create new product advantages and reshape competitive dynamics in technology-related markets.

sram technical

"nanostack architecture provides 40 percent scaling in SRAM,2 unlocking the ability"

Static random-access memory (SRAM) is a fast type of computer memory that stores data instantly and reliably while power is on, similar to a small, very quick notepad a processor keeps next to it. Investors care because SRAM influences product speed, power use, cost and production capacity for electronics and semiconductor companies, affecting profit margins, competitive positioning and supply-chain risk.

high numerical aperture extreme ultraviolet technical

"home to a High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography tool,"

High numerical aperture extreme ultraviolet (high-NA EUV) is an advanced chipmaking optical technology that uses a wider-angle, higher-precision lens system with extreme ultraviolet light to print much finer patterns on semiconductor wafers. For investors, it matters because it enables manufacturers to produce denser, faster and more energy-efficient chips, driving big capital spending, shaping equipment supplier winners and influencing future product performance and profitability—think of upgrading from a standard camera lens to a pro lens that reveals far more detail.

AI-generated analysis. Not financial advice.

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Built with revolutionary "nanostack" 3D chip architecture, IBM's sub-1 nm chip to propel semiconductor industry forward for the next decade

YORKTOWN HEIGHTS, N.Y., June 25, 2026 /PRNewswire/ -- IBM (NYSE: IBM) today unveiled a major semiconductor breakthrough with the introduction of the world's first sub-1 nanometer (nm) chip technology, featuring a revolutionary transistor architecture at the 0.7 nm, or 7 angstrom node. The achievement marks a landmark moment for an industry facing the physical limits of traditional chip scaling. Semiconductors play critical roles in everything from computing, to appliances, to communication devices, transportation systems, and critical infrastructure.

IBM's new sub-1 nm chip packs nearly 100 billion transistors onto a chip the size of a fingernail, nearly twice the density of IBM's 2 nm chip, unveiled in 2021. Enabled by a series of structural and material innovations, including IBM's groundbreaking three-dimensional nanostack architecture, the technology demonstrates how continued gains in performance and efficiency remain possible even as chip features approach atomic dimensions. 

Published technical results report the new chip is projected to offer a substantial leap in capability—up to 50 percent more performance, or 70 percent greater energy efficiency than IBM's 2 nm node chips¹—supercharging compute for applications ranging from generative AI and cloud infrastructure to next-generation electronic devices.

"IBM's latest chip breakthrough marks a landmark moment in computing, pushing technology beyond the nanometer era to the scale of atoms. With our new nanostack architecture, we're not just making smaller transistors, we're reinventing how chips are built to deliver dramatically more power and energy efficiency," said Jay Gambetta, Director of IBM Research and IBM Fellow. "This industry-first innovation continues IBM's legacy of leading in next-generation technologies and sets the foundation for the next era of computing."

Nanostack, an Industry Breakthrough in Chip Design

To produce this chip, IBM researchers developed an entirely new transistor architecture, called "nanostack," the industry's first known three-dimensional, nanosheet-based design. Nanostack represents a major advance beyond nanosheet technology, the industry's current leading-edge architecture, invented by IBM. The nanostack design vertically stacks and staggers transistors, taking advantage of 3D sequential integration to pack more transistors onto a chip. The design also unlocks the use of different material combinations within each stacked layer, optimizing performance and power efficiency of each transistor independent of the other.

IBM's nanostack architecture was experimentally validated through ultra-thin dielectric bonding in CMOS integration, demonstration of dual-channel engineering capability, and functional CMOS inverter operation with expected switching performance. Together, these results confirm the nanostack technology can be physically built and supports real computation.

Additionally, in new research presented at VLSI 2026, IBM researchers demonstrated that the nanostack architecture provides 40 percent scaling in SRAM,² unlocking the ability of chip designers to create much more efficient chips while also supporting the high-bandwidth data demands of advanced AI workloads.

With this groundbreaking structure, logic technology can extend for the first time below the 1 nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM's 0.7 nm technology—also referred to as 7 angstroms—demonstrates how continued scaling remains possible. With the new nanostack architecture, IBM's semiconductor roadmap projects at least a decade of future scaling.

Building on Decades of Leadership in Semiconductor Innovation

This breakthrough is the latest testament to IBM as a leader in semiconductor R&D. IBM has led the world in developing the chips that power computing systems for decades, from early semiconductors in the 1960s to the world's first 2 nm node chip. IBM continues to innovate at the cutting edge of silicon, AI hardware, logic, and quantum processors developed to power the future of computing.

IBM and its partners conduct this work at a leading semiconductor research facility in Albany, New York, which will soon be home to a High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography tool, essential for the future of logic scaling. Developed by ASML, this technology enables ultra‑precise circuit printing, supporting the creation of smaller, more powerful chips. IBM and partners including Lam Research Corp., Tokyo Electron (TEL), and SCREEN Semiconductor Solutions, Ltd. have been working together to develop new High NA EUV processes and tools that have already yielded working devices.

IBM also recently announced a plan to form Anderon, the world's first pure-play quantum foundry. Anderon, a standalone IBM company, will draw on IBM's industry-leading quantum computing and semiconductor expertise to help position the United States to manufacture most of the world's quantum wafers.

With the expectation of the earliest adoption of nanostack technology at the sub-1 nm node, IBM sees a path to production in as early as the next 5 years.

About IBM

IBM is a leading provider of global hybrid cloud and AI, and consulting expertise. We help clients in more than 175 countries capitalize on insights from their data, streamline business processes, reduce costs and gain the competitive edge in their industries. More than 4,000 government and corporate entities in critical infrastructure areas such as financial services, telecommunications and healthcare rely on IBM's hybrid cloud platform and Red Hat OpenShift to affect their digital transformations quickly, efficiently and securely. IBM's breakthrough innovations in AI, quantum computing, industry-specific cloud solutions and consulting deliver open and flexible options to our clients. All of this is backed by IBM's long-standing commitment to trust, transparency, responsibility, inclusivity and service. Visit www.ibm.com for more information.

Media Contacts

Willa Hahn
IBM Communications
willa.hahn@ibm.com

Brittany Forgione
IBM Communications
brittany.forgione@ibm.com

¹ S. Reboh et al "NanoStack Transistor Architecture for CMOS 7A Node and Beyond" VLSI 2025

² Chen Zhang et al "Area and Performance of Staggered-Channel Nanostack SRAM Bitcells" VLSI 2026

View original content to download multimedia:https://www.prnewswire.com/news-releases/ibm-debuts-worlds-first-sub-1-nanometer-chip-technology-302809961.html

SOURCE IBM

FAQ

What did IBM (NYSE:IBM) announce about sub-1 nanometer chip technology on June 25, 2026?

IBM unveiled the world’s first sub-1 nanometer chip technology at the 0.7 nm (7 angstrom) node. According to IBM, the nanostack-based design targets significantly higher performance and efficiency for applications like generative AI, cloud infrastructure, and next-generation electronic devices.

How many transistors does IBM’s new 0.7 nm chip technology integrate on a single chip?

IBM’s sub-1 nm chip integrates nearly 100 billion transistors on a fingernail-sized chip. According to IBM, this is about twice the transistor density of its earlier 2 nm chip, enabling more powerful and energy-efficient computing in the same physical footprint.

How does IBM’s 0.7 nm nanostack chip compare to its 2 nm node in performance and efficiency?

IBM projects the 0.7 nm nanostack chip can deliver up to 50% more performance or 70% greater energy efficiency than its 2 nm node. According to IBM, these gains come from 3D stacked nanosheet transistors and material optimizations in each layer.

What is IBM’s nanostack architecture and why is it important for IBM (IBM) investors?

Nanostack is a three-dimensional, nanosheet-based transistor architecture that vertically stacks and staggers transistors. According to IBM, it enables higher transistor density, independent power-performance tuning per layer, and extends logic technology below the 1 nm node, supporting at least a decade of further scaling.

When could IBM’s sub-1 nm nanostack technology reach production, and what is the timeline?

IBM currently sees a path to production for its nanostack technology in as early as the next five years. According to IBM, this timeline positions the company to support future high-performance computing, AI, and advanced logic needs as scaling continues.

How does IBM’s 0.7 nm nanostack technology affect AI and high-bandwidth workloads?

IBM reports that nanostack enables 40% SRAM scaling, improving on-chip memory density. According to IBM, this helps designers build more efficient chips that better handle high-bandwidth data demands from advanced AI workloads and modern cloud infrastructure.

What role do IBM’s research partnerships play in advancing its sub-1 nm chip roadmap?

IBM collaborates with partners in its Albany, New York semiconductor research facility and on High NA EUV tools. According to IBM, these partnerships have already yielded working devices and support development of processes required for future nanostack-based logic scaling.