Keysight to Showcase Advanced AI Data Center and High-Speed Interconnect Validation at DesignCon 2026

Key Terms

chiplet technical

A chiplet is a small, specialized piece of a computer chip designed to be combined with other chiplets on a single package to create a larger, complete processor — think of it like Lego bricks that snap together to build different models. For investors, chiplets matter because they can lower manufacturing costs, improve production yields, and speed innovation by letting designers mix and match proven building blocks, affecting profit margins and competitive position in the semiconductor industry.

3d ic technical

A 3D IC is a semiconductor chip made by stacking multiple layers of circuitry vertically and electrically linking them so they function as a single unit, like stacking floors in a building instead of spreading everything across a single floor. For investors, 3D ICs can deliver faster speeds, lower power use and smaller devices, which can boost product competitiveness, affect manufacturing costs and influence a company’s growth prospects.

ddr5 technical

DDR5 is the latest generation of high-speed volatile memory used as the short-term workspace for computers and servers, like a faster, larger desk where a processor keeps information it’s actively using. It matters to investors because upgrades to DDR5 drive demand across chip makers, computer builders and data-centre operators, affecting sales, pricing power and product cycles; companies that lead in DDR5 production or adoption can gain a competitive and financial edge.

pam4 technical

PAM4 is a digital signaling method that sends information by using four distinct voltage or light levels instead of the usual two, letting each transmitted symbol carry two bits of data. Think of it like a radio knob with four clear positions instead of just on/off; it boosts transmission speed without needing extra wires or spectrum but is harder to read reliably, so it matters to investors because it drives demand for higher-performance chips, better cables and optics, and can affect product costs, margins and upgrade cycles in networking and data-center markets.

SANTA ROSA, Calif.--(BUSINESS WIRE)-- Keysight Technologies, Inc. (NYSE: KEYS):

What: Keysight will showcase end-to-end solutions enabling AI system design, interoperability validation, and large-scale performance at DesignCon 2026. From advanced packaging and chiplets to PCIe®, memory, and USB4 validation, the demos demonstrate how to overcome physical limits, ensure compliance, and de-risk designs early. The journey culminates with 1.6T interconnect benchmarking and validation of emerging AI fabrics, giving customers confidence their designs will perform at system scale while accelerating time to deployment.

When: February 24-26, 2026

Where: Keysight Booth (number 1039)

Santa Clara Convention Center

Media: Contact Andrea Mueller to schedule media briefings and solution demonstrations

Info: Keysight will participate in 16 paper, panel, and tutorial presentations, as well as nine talks, via the Keysight Educational Forum on Feb. 25 in the Great America K Ballroom.

Demonstrations include:

• Chiplet 3D Interconnect Designer: Demonstrates a chiplet and 3D IC design workflow that accelerates multi-die interconnect development for AI and high-performance devices.
• Signal Integrity at 3.2T Speeds: The demo pairs the Physical Layer Test System (PLTS2026) with the NA5307A Frequency Extender (250 GHz) and supporting tools to show the bandwidth and accuracy needed for next-generation infrastructure validation, helping accelerate time-to-market.
• Next Generation Memory Validation: Highlights measurement solutions for AI workloads through memory demos, including a live DDR5 system for mainstream electrical validation and a GDDR7 PAM3 signal integrity setup utilizing the new SNDR and jitter measurement suite to streamline compliance and debug.
• Reliable PCIe^® PAM4 Performance: Showcases Keysight’s next-generation PCIe test solutions for PCIe 7.0, spanning both electrical (PHY) and protocol-layer validation. The demo highlights how the UXR-Series oscilloscope, M8050A BERT platform, and PCIe test software accelerate debug, improve margin analysis, and enhance link reliability.
• 448 Gbps Pathfinding: This solution advances signal integrity research by leveraging the M8199B arbitrary waveform generator and the N1046A electrical channel module to generate and analyze PAM4, PAM6, and PAM8 signals. Together, they enable researchers to evaluate signaling trade-offs and optimize modulation strategies for next-generation interconnect architectures.
• 1.6T Interconnects for AI Networks: Demonstrates how the Keysight INPT-1600GE benchtop test system helps engineers ensure performance and reliability by validating BER and FEC, measuring link quality, and benchmarking AI workloads
• UALink and Scale-Up Ethernet for AI Infrastructure: Highlights Keysight’s automation, validation, and compliance solutions for 1.6T-class electrical networking interfaces, enabling automated test workflows, expanded measurement coverage, and streamlined calibration for conformance and debug.

About Keysight Technologies

At Keysight (NYSE: KEYS), we inspire and empower innovators to bring world-changing technologies to life. As an S&P 500 company, we're delivering market-leading design, emulation, and test solutions to help engineers develop and deploy faster, with less risk, throughout the entire product life cycle. We're a global innovation partner enabling customers in communications, industrial automation, aerospace and defense, automotive, semiconductor, and general electronics markets to accelerate innovation to connect and secure the world. Learn more at Keysight Newsroom and www.keysight.com.

View source version on businesswire.com: https://www.businesswire.com/news/home/20260209459831/en/

Andrea Mueller

andrea.mueller@keysight.com

Source: Keysight Technologies, Inc.