QuickLogic Unveils Next-Generation eFPGA Hard IP for GlobalFoundries 12LP

QuickLogic (QUIK) introduced an enhanced next-generation eFPGA Hard IP for GlobalFoundries 12LP, targeting compute-intensive and high-reliability system-on-chip designs.

Rhea-AI Summary

QuickLogic (QUIK) introduced an enhanced next-generation eFPGA Hard IP for GlobalFoundries 12LP, targeting compute-intensive and high-reliability system-on-chip designs.

The new release adds an upgraded DSP Multiply-and-Accumulate unit with preadder, cascade connections, and SIMD support for applications such as phased array radar, electronic warfare, wireless infrastructure, satellite communications, and imaging. The eFPGA fabric now scales beyond 250,000 LUTs to address larger embedded programmable logic needs. An optional Configuration Bit Health Monitor detects and corrects Single Event Upset–induced configuration bit errors during operation to support applications requiring near-real-time configuration integrity. The IP is supported by QuickLogic’s Aurora and AuroraPRO tool flows, and will be showcased at GlobalFoundries Technology Summit (GTS) North America on September 2, 2026 at the Santa Clara Marriott, booth #11.

Market Context

QUIK recorded -7.94% after the August 11 earnings report. This history adds context for separating t...

Analysis

QUIK recorded -7.94% after the August 11 earnings report. This history adds context for separating technical capability from financial validation; the S-3 shelf was not effective, and no recent insider activity was reported.

Key Figures

eFPGA scale: >250,000 LUTs Process technology: 12LP Summit date: September 2, 2026

3 metrics

eFPGA scale >250,000 LUTs GF 12LP embedded programmable logic fabric

Process technology 12LP GlobalFoundries eFPGA Hard IP

Summit date September 2, 2026 GlobalFoundries Technology Summit North America

Historical Context

5 past events · Latest: Aug 11 (Positive)

Pattern 5 events

Date	Event	Sentiment	24h Move	Catalyst
Aug 11	Q2 earnings report	Positive	-7.9%	Revenue growth and improved margins accompanied a reported quarterly loss.
Jul 28	Earnings date notice	Neutral	-4.7%	Company scheduled second-quarter results and listed upcoming investor conferences.
Jul 16	Technical collaboration	Positive	-8.1%	Collaboration demonstrated post-quantum cryptography mapping onto QuickLogic eFPGA.
Jun 16	Conference participation	Neutral	-4.6%	Management announced participation in the Northland Growth Conference.
Jun 2	Index inclusion	Positive	+5.6%	QuickLogic announced inclusion in the Russell 2000 and Russell 3000 indexes.

24h Move is the share-price change in the day after each event; other market factors may also have contributed.

Pattern Detected

QUIK diverged from favorable or informational news in four of five recent events, with only the June 2 index-inclusion announcement aligning with a positive reaction.

Key Terms

efpga hard ip, multiply-and-accumulate, single event upsets

3 terms

efpga hard ip technical

"The enhanced eFPGA Hard IP builds on QuickLogic's silicon-proven technology"

eFPGA hard IP is a pre-designed, silicon-optimized intellectual property block that implements a field-programmable gate array (FPGA) fabric as a fixed physical block ready to be integrated into an ASIC or system-on-chip. It matters to investors because it changes how chipmakers add reprogrammability—offering predictable performance, area and power characteristics, licensing fees and faster product integration—much like buying a finished engine to install in a car rather than designing one from scratch.

multiply-and-accumulate technical

"A new DSP Multiply-and-Accumulate (MAC) unit"

A multiply-and-accumulate (MAC) is a single computing operation that multiplies two numbers and adds the result into a running total, commonly used in digital signal processing, graphics and machine‑learning calculations. It matters to investors because the speed, number and energy efficiency of MAC units in a chip determine how quickly and cheaply that hardware can perform workloads such as AI inference or video processing—think of it like how many items a cashier can scan and total per minute.

single event upsets technical

"configuration bit errors induced by Single Event Upsets (SEUs)"

A single event upset (SEU) is a temporary change of state in electronic circuitry caused when a high-energy particle—such as a cosmic ray or radiation particle—strikes a semiconductor device and flips a stored bit or logic state. It matters to investors because SEUs affect the reliability and safety of products used in satellites, aviation, medical devices and other critical systems, which can drive design costs, warranty exposure, regulatory scrutiny and customer trust; think of it as a random glitch that can break digital memory or logic.

AI-generated analysis. How Rhea-AI works. Not financial advice.

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- New release delivers improved performance and area efficiency, scales beyond 250K LUTs, and adds enhanced DSP and optional configuration bit health monitoring

SAN JOSE, Calif., Sept. 2, 2026 /PRNewswire/ -- The enhanced eFPGA Hard IP builds on QuickLogic's silicon-proven technology for GF 12LP and expands its capabilities for compute-intensive and high-reliability applications. Key new features include:

• Enhanced signal processing: A new DSP Multiply-and-Accumulate (MAC) unit, with enhanced preadder, cascade connections, and SIMD functionality, provides greater support for phased array radar, electronic warfare, wireless infrastructure, satellite communications, and imaging algorithms.
• Scalability beyond 250K LUTs: The eFPGA fabric can scale to support more than 250,000 LUTs, addressing designs with larger embedded programmable logic requirements.
• Optional Configuration Bit Health Monitor: Detects and corrects configuration bit errors induced by Single Event Upsets (SEUs) while the eFPGA user design is active, supporting applications where near-real-time configuration integrity and system reliability are paramount.

"Customers increasingly want the flexibility to adapt hardware functions after tape-out without sacrificing the performance, power and area advantages of an ASIC," said Andy Jaros, VP of IP Sales at QuickLogic. "Our enhanced eFPGA Hard IP for GF 12LP gives SoC developers greater scalability and signal-processing capability, while our optional Configuration Bit Health Monitor adds another level of reliability for the most demanding applications."

QuickLogic's eFPGA Hard IP enables programmable logic to be embedded directly within an SoC, allowing critical hardware functions, algorithms and interfaces to be updated post-manufacturing. The architecture can be scaled and configured with user-defined combinations of LUT, BlockRAM and DSP resources to address a range of applications, with complete RTL-to-bitstream development support through QuickLogic's Aurora™ and AuroraPRO™ tools.

Learn More at GTS North America

QuickLogic is a Silver Sponsor of GlobalFoundries Technology Summit (GTS) North America. Attendees can meet with the QuickLogic team to learn more about the enhanced GF 12LP eFPGA Hard IP and QuickLogic's embedded FPGA solutions.

What:	GlobalFoundries Technology Summit (GTS) North America
Location:	Santa Clara Marriott in Santa Clara, CA
Booth:	#11 in the Partner Pavilion
Date:	September 2, 2026

For more information about QuickLogic eFPGA Hard IP, visit www.quicklogic.com.

About QuickLogic 

QuickLogic is a fabless semiconductor company specializing in embedded FPGA (eFPGA) Hard IP, Strategic Radiation Hardened and Antifuse FPGAs, and ruggedized programmable logic solutions. QuickLogic's unique approach combines cutting-edge technology with open-source tools to deliver highly customizable low-power solutions for aerospace and defense, industrial, computing, and consumer markets. For more information, visit www.quicklogic.com.

QuickLogic and logo are registered trademarks of QuickLogic. All other trademarks are the property of their respective holders and should be treated as such.

 

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SOURCE QuickLogic Corporation

FAQ

What did QuickLogic (QUIK) announce about its next-generation eFPGA Hard IP for GF 12LP?

QuickLogic announced an enhanced eFPGA Hard IP for GlobalFoundries 12LP that improves performance and area efficiency, scales beyond 250K LUTs, and introduces enhanced DSP capabilities plus an optional Configuration Bit Health Monitor for higher reliability in compute-intensive applications.

How does the new QuickLogic (QUIK) eFPGA Hard IP improve DSP and signal processing?

The enhanced eFPGA Hard IP includes a new DSP Multiply-and-Accumulate (MAC) unit with an enhanced preadder, cascade connections, and SIMD functionality, providing greater support for phased array radar, electronic warfare, wireless infrastructure, satellite communications, and imaging algorithms.

What is the purpose of the Configuration Bit Health Monitor in QuickLogic’s new eFPGA Hard IP (QUIK)?

The optional Configuration Bit Health Monitor detects and corrects configuration bit errors caused by Single Event Upsets while the eFPGA user design is active, supporting applications where near-real-time configuration integrity and overall system reliability are critical.

Where and when will QuickLogic (QUIK) showcase its enhanced GF 12LP eFPGA Hard IP?

QuickLogic will showcase the enhanced GF 12LP eFPGA Hard IP at the GlobalFoundries Technology Summit (GTS) North America on September 2, 2026, at the Santa Clara Marriott in Santa Clara, CA, at booth #11 in the Partner Pavilion.

How can developers use QuickLogic’s eFPGA Hard IP (QUIK) within their SoC designs?

QuickLogic’s eFPGA Hard IP embeds programmable logic directly in an SoC, enabling post-manufacturing updates of hardware functions and algorithms. The architecture is configurable with user-defined mixes of LUT, BlockRAM, and DSP resources, with RTL-to-bitstream support through Aurora and AuroraPRO tools.