Welcome to our dedicated page for Synopsys news (Ticker: SNPS), a resource for investors and traders seeking the latest updates and insights on Synopsys stock.
Synopsys Inc (NASDAQ: SNPS) drives innovation in electronic design automation (EDA) and semiconductor IP solutions, enabling next-generation chip and system development. This dedicated news hub provides investors and industry professionals with official announcements, strategic updates, and market insights directly from Synopsys leadership.
Comprehensive Coverage: Access timely updates including quarterly earnings reports, product launch details, technology partnerships, and executive commentary. Our curated collection features verified press releases covering critical developments in EDA software advancements, silicon IP licensing agreements, and software security innovations.
Strategic Resource: Track Synopsys' role in shaping semiconductor design trends through acquisitions, R&D milestones, and industry collaborations. Stay informed about developments impacting automotive electronics, AI hardware acceleration, and cloud-based design tools—key growth areas in modern computing infrastructure.
Bookmark this page for immediate access to Synopsys' latest corporate communications and technology announcements. Check regularly for updates that matter to semiconductor investors, engineering professionals, and technology analysts worldwide.
Synopsys has launched Euclide, a next-generation integrated development environment (IDE) that enhances hardware description language (HDL) coding. It enables early bug detection and optimizes design compliance checks during SystemVerilog and UVM development. Key features include real-time checks, integration with Verdi, and support for VCS simulation, improving overall code quality and engineering efficiency. The solution is currently available and aims to address the growing complexity in system-on-chip designs.
Synopsys, Inc. (Nasdaq: SNPS) has launched the ZeBu® Empower emulation system, the first power-aware solution for multi-billion gate designs, aimed at facilitating hardware-software power verification. This technology allows for rapid iterations of power profiling, enhancing the design cycle efficiency and reducing risks associated with post-silicon power analysis. Key partnerships include collaborations with AMD and SiMa.ai, demonstrating significant advancements in pre-silicon power analysis capability.
Synopsys, Inc. (Nasdaq: SNPS) announced that its co-CEO Aart de Geus will be speaking at the 2021 Virtual Morgan Stanley Technology, Media and Telecom Conference on March 2, 2021, at 9:30 a.m. PT (12:30 p.m. ET). The event will be available for live streaming on the Synopsys corporate website. A replay of the presentation will be accessible about an hour after the live event and will remain available for six months.
Synopsys (Nasdaq: SNPS) announced certification of its IC Validator physical verification solution by Samsung Foundry for advanced 5-nanometer and 4nm technologies. This solution is part of Synopsys' Fusion Design Platform and Custom Design Platform, enhancing productivity and accuracy in chip design. The technology facilitates quick DRC checks and supports complex designs with numerous rules and operations. According to Samsung's Jongwook Kye, the IC Validator is crucial for achieving silicon success in demanding applications.
Synopsys, Inc. (SNPS) reported strong results for Q1 FY2021, with revenue of $970.3 million, up from $834.4 million in Q1 FY2020. The company achieved net income of $162.3 million (GAAP) or $1.03 per share, and $239.5 million (non-GAAP) or $1.52 per share, reflecting growth across its segments. Synopsys initiated a $250 million stock repurchase and reaffirmed its full-year outlook, anticipating revenue surpassing $4 billion and non-GAAP EPS growth in the low-to-mid teens.
Synopsys (Nasdaq: SNPS) announced that CFO Trac Pham will present at the Virtual KeyBanc Capital Markets 2021 Emerging Technology Summit on February 23, 2021, at 3:25 p.m. ET. The event will be streamed live on the Synopsys corporate website, with a replay available after the live event for four months. Synopsys is a leader in electronic design automation and semiconductor IP, offering tools for secure software applications and advanced semiconductor designs.
Synopsys, Inc. (Nasdaq: SNPS) has been awarded the Customers' Choice Award for a technical paper presented at the TSMC 2020 North America Open Innovation Platform Ecosystem Forum. The paper, titled "5nm Node Enablement and Maximizing QoR Using Fusion Compiler," was developed by Henry Sheng and recognized based on attendee votes. TSMC officials expressed appreciation for Synopsys' commitment to sharing expertise and collaboration in advancing silicon innovations for markets like 5G and automotive. This recognition underscores Synopsys' contribution to the TSMC ecosystem and its innovative solutions.
Synopsys (Nasdaq: SNPS) announces its collaboration with Microsoft on the Rapid Assured Microelectronics Prototypes (RAMP) program. This partnership aims to develop integrated circuit hardware prototypes that ensure security in design and manufacturing within Microsoft Azure. The RAMP initiative seeks to enhance semiconductor innovation for government applications, allowing for trusted design and verification solutions. Additionally, Synopsys is also collaborating with the U.S. Government to enhance security in integrated circuit devices through the Automatic Implementation of Secure Silicon (AISS) program.
Synopsys (Nasdaq: SNPS) will announce its first quarter fiscal year 2021 results on Feb. 17, 2021, after market close. A conference call featuring Aart de Geus and Trac Pham will commence at 2:00 p.m. PT (5:00 p.m. ET) to discuss the results. Financial information will be available on their corporate website prior to the call, and a live webcast will also be offered. A replay of the conference call will be accessible from 4:00 p.m. PT on the same day until the announcement of the second quarter results in May 2021.
Synopsys, Inc. (Nasdaq: SNPS) has demonstrated silicon proof of its DesignWare 112G Ethernet PHY IP in a 5nm FinFET process. This technology enhances performance, power efficiency, and area optimization for system-on-chip (SoC) designs. The DesignWare 112G PHY boasts zero bit-error rate in channels over 40dB, with power efficiency below five picojoules per bit. Synopsys combines this innovation with comprehensive support, including routing feasibility studies and signal integrity models, providing a robust solution for high-performance cloud computing applications.