Welcome to our dedicated page for Synopsys news (Ticker: SNPS), a resource for investors and traders seeking the latest updates and insights on Synopsys stock.
Synopsys Inc. reports developments across electronic design automation, semiconductor intellectual property, silicon design, simulation and analysis solutions, and design services. Company news commonly covers AI-powered design flows, hardware-assisted verification, interface IP, multiphysics simulation, digital twin capabilities, and engineering software that supports chip, system, and product development.
Recurring updates also include customer and ecosystem work with semiconductor foundries, processor and GPU platforms, cloud infrastructure, aerospace programs, and other engineering users. Financial news centers on earnings releases, business outlook commentary, share repurchase activity, and the integration of Synopsys and Ansys technologies within the company’s expanded silicon-to-systems portfolio.
Synopsys, Inc. (Nasdaq: SNPS) will announce its third quarter fiscal year 2020 results on August 19, 2020, after market close. A conference call featuring Aart de Geus and Trac Pham will start at 2:00 p.m. PT (5:00 p.m. ET). Financial details will be accessible on the corporate website prior to the call. Participants can access a live webcast and a replay of the call. Synopsys is recognized as a leader in electronic design automation and semiconductor IP, supporting various industries in developing secure, high-quality products.
Synopsys, Inc. (Nasdaq: SNPS) announces the appointment of Jason Schmitt as general manager of the Software Integrity Group. Schmitt, a seasoned leader with over 20 years of experience, has previously been CEO of Aporeto and held key roles at major tech companies. Synopsys aims to scale its Software Integrity business from over $300 million towards $500 million to $1 billion in revenue. Schmitt's expertise is expected to address emerging cybersecurity challenges and enhance the company's strategic goals in application security amidst the evolving DevOps landscape.
Synopsys, Inc. (Nasdaq: SNPS) announces that Aart de Geus, co-CEO, will speak at the 50th annual SEMICON West 2020 conference. The conference is set for July 23, 2020, at 8:00 a.m. PT (11:00 a.m. ET) and will be broadcast live online via the SEMICON West portal. Media interested in registration can contact Scott Stevens at Cardinal Communications for SEMI Americas.
As a leader in electronic design automation and semiconductor IP, Synopsys offers critical solutions for companies developing innovative electronic products and software applications.
Synopsys (Nasdaq: SNPS) announced that Graphcore utilized its VCS® simulation solution alongside Verdi® debug to verify the Colossus™ GC200 Intelligence Processing Unit, touted as the most complex microprocessor with 59.4Bn transistors and 1,472 cores. The collaboration significantly enhanced simulation performance, offering 2X to 5X gains compared to single-core architectures. This productivity boost enables accelerated time-to-market for AI chip designs, crucial for staying competitive in the rapidly evolving market.
Synopsys (Nasdaq: SNPS) announces Tenstorrent's achievement of first-pass silicon success for its Grayskull AI processor SoC, utilizing Synopsys' DesignWare PCI Express 4.0, ARC HS48 Processor, and LPDDR4 IP. This SoC delivers high-performance computing capabilities with low-latency connections, handling significant channel loss. Tenstorrent plans to collaborate with Synopsys for future AI processor SoCs aimed at data centers, cloud servers, and automotive markets. The DesignWare IP portfolio facilitated swift integration and reduced design timelines for Tenstorrent.
Synopsys (Nasdaq: SNPS) has launched the first JEDEC DDR5 compliant Verification IP for DDR5 DRAM/DIMM, aimed at enhancing memory performance in cloud, IoT, and data centers. This technology supports data rates from 3200MT/s to 8400MT/s, with improved density and power efficiency. The VC VIP for DDR5 enables simpler integration and faster verification processes, optimized for next-gen memory architecture. Available now, it promises significant advancements for companies needing high-memory bandwidth. The collaboration with Micron further strengthens confidence in this product.
Synopsys, Inc. (Nasdaq: SNPS) announced that JLQ Technology has adopted its DesignWare IP portfolio to enhance development speed and reduce risks for new mobile chipsets. The collaboration aims for next-generation systems-on-chips (SoCs) optimized for performance and power efficiency. Synopsys' track record has facilitated volume production for JLQ's previous SoC designs. Key technologies include USB, MIPI, and DDR, which are essential for intelligent IoT applications.
Synopsys (Nasdaq: SNPS) has entered a multi-year agreement with Arm to accelerate the design and verification of Arm-based system-on-chips (SoCs). This collaboration will enhance Synopsys products, including the Fusion Design Platform and Verification Continuum Platform, by integrating them with Arm IP. Synopsys will gain early access to a variety of Arm processors and GPUs, which aims to optimize design methodologies for mutual customers across diverse markets. This partnership continues a nearly 30-year relationship between the two companies.
Synopsys (Nasdaq: SNPS) has expanded its collaboration with EPFL, the Swiss Federal Institute of Technology, to license new digital synthesis technologies. This partnership aims to develop advanced Electronic Design Automation (EDA) and Technology Computer Aided Design (TCAD) tools for superconducting electronics (SCE) under IARPA's SuperTools project. EPFL's new methods could reduce power requirements for electronic chips by optimizing logic flow, potentially decreasing logic levels by an average of 18%. This innovation may lead to faster and more energy-efficient chip designs.
Synopsys (Nasdaq: SNPS) has been selected by DARPA as a prime contractor for the Automatic Implementation of Secure Silicon (AISS) program aimed at automating hardware security mechanisms in SoCs. The four-year project will see collaboration with experts from Arm, Boeing, and various universities. Synopsys will provide DesignWare® Security IP and develop design-to-manufacturing flows to optimize power, area, speed, and security. The collaboration underscores Synopsys' commitment to enhancing security in microelectronics, benefiting both defense and commercial sectors.