Synopsys and TSMC Usher In Angstrom-Scale Designs with Certified EDA Flows on Advanced TSMC A16 and N2P Processes
Synopsys (SNPS) has announced an expanded collaboration with TSMC to deliver advanced EDA and IP solutions for TSMC's cutting-edge processes. The partnership focuses on certified digital and analog flows for TSMC A16™ and N2P processes, powered by Synopsys.ai.
Key developments include early collaboration on TSMC A14 process, support for 3Dblox and TSMC's CoWoS® technologies enabling 5.5x reticle size packages, and a comprehensive IP portfolio offering the lowest power consumption on TSMC's N2/N2P processes. The collaboration features complete IP solutions for advanced standards like HBM4, 1.6T Ethernet, UCIe, PCIe 7.0, and UALink.
The partnership enhances 3DIC Compiler capabilities, supporting ultra-high-density interconnects and increased productivity for multi-die designs. The solution integrates multi-physics analysis and Ansys simulation technologies for comprehensive power, thermal, and signal integrity analysis.
Synopsys (SNPS) ha annunciato una collaborazione ampliata con TSMC per offrire soluzioni avanzate di EDA e IP dedicate ai processi all'avanguardia di TSMC. La partnership si concentra su flussi digitali e analogici certificati per i processi TSMC A16™ e N2P, supportati da Synopsys.ai.
Tra gli sviluppi principali vi sono la collaborazione anticipata sul processo TSMC A14, il supporto per le tecnologie 3Dblox e CoWoS® di TSMC che permettono pacchetti con dimensioni reticolo 5,5 volte maggiori, e un portafoglio IP completo che garantisce il consumo energetico più basso sui processi N2/N2P di TSMC. La collaborazione offre soluzioni IP complete per standard avanzati come HBM4, Ethernet 1.6T, UCIe, PCIe 7.0 e UALink.
La partnership potenzia le capacità del 3DIC Compiler, supportando interconnessioni ultra-dense e aumentando la produttività per progetti multi-die. La soluzione integra analisi multifisiche e tecnologie di simulazione Ansys per un’analisi completa di potenza, termica e integrità del segnale.
Synopsys (SNPS) ha anunciado una colaboración ampliada con TSMC para ofrecer soluciones avanzadas de EDA e IP para los procesos de vanguardia de TSMC. La alianza se centra en flujos digitales y analógicos certificados para los procesos TSMC A16™ y N2P, impulsados por Synopsys.ai.
Los desarrollos clave incluyen la colaboración temprana en el proceso TSMC A14, soporte para las tecnologías 3Dblox y CoWoS® de TSMC que permiten paquetes con un tamaño de retícula 5.5 veces mayor, y un portafolio integral de IP que ofrece el menor consumo energético en los procesos N2/N2P de TSMC. La colaboración presenta soluciones IP completas para estándares avanzados como HBM4, Ethernet 1.6T, UCIe, PCIe 7.0 y UALink.
La alianza mejora las capacidades del 3DIC Compiler, apoyando interconexiones de ultra alta densidad y aumentando la productividad en diseños multi-die. La solución integra análisis multiphysics y tecnologías de simulación Ansys para un análisis exhaustivo de potencia, térmico e integridad de señal.
Synopsys (SNPS)는 TSMC와의 협력을 확대하여 TSMC의 최첨단 공정을 위한 고급 EDA 및 IP 솔루션을 제공한다고 발표했습니다. 이번 파트너십은 Synopsys.ai를 기반으로 TSMC A16™ 및 N2P 공정에 대한 인증된 디지털 및 아날로그 플로우에 중점을 둡니다.
주요 개발 사항으로는 TSMC A14 공정에 대한 초기 협력, 5.5배 큰 리티클 크기 패키지를 가능하게 하는 3Dblox 및 TSMC의 CoWoS® 기술 지원, 그리고 TSMC N2/N2P 공정에서 가장 낮은 전력 소비를 제공하는 포괄적인 IP 포트폴리오가 포함됩니다. 이 협력은 HBM4, 1.6T 이더넷, UCIe, PCIe 7.0, UALink와 같은 첨단 표준에 대한 완전한 IP 솔루션을 제공합니다.
파트너십은 3DIC Compiler의 기능을 강화하여 초고밀도 인터커넥트와 멀티 다이 설계의 생산성 향상을 지원합니다. 이 솔루션은 다중 물리 분석과 Ansys 시뮬레이션 기술을 통합하여 전력, 열, 신호 무결성에 대한 종합적인 분석을 제공합니다.
Synopsys (SNPS) a annoncé une collaboration élargie avec TSMC pour fournir des solutions avancées d’EDA et d’IP pour les procédés de pointe de TSMC. Ce partenariat se concentre sur des flux numériques et analogiques certifiés pour les procédés TSMC A16™ et N2P, propulsés par Synopsys.ai.
Les développements clés incluent une collaboration précoce sur le procédé TSMC A14, le support des technologies 3Dblox et CoWoS® de TSMC permettant des packages de taille réticulaire 5,5 fois plus grands, ainsi qu’un portefeuille IP complet offrant la consommation d’énergie la plus basse sur les procédés N2/N2P de TSMC. Cette collaboration propose des solutions IP complètes pour des standards avancés tels que HBM4, Ethernet 1.6T, UCIe, PCIe 7.0 et UALink.
Le partenariat améliore les capacités du 3DIC Compiler, supportant des interconnexions ultra-haute densité et augmentant la productivité pour les conceptions multi-die. La solution intègre une analyse multiphysique et les technologies de simulation Ansys pour une analyse complète de la puissance, thermique et intégrité du signal.
Synopsys (SNPS) hat eine erweiterte Zusammenarbeit mit TSMC angekündigt, um fortschrittliche EDA- und IP-Lösungen für die hochmodernen Prozesse von TSMC bereitzustellen. Die Partnerschaft konzentriert sich auf zertifizierte digitale und analoge Flows für die TSMC A16™- und N2P-Prozesse, unterstützt von Synopsys.ai.
Zu den wichtigsten Entwicklungen zählen die frühe Zusammenarbeit am TSMC A14-Prozess, die Unterstützung der 3Dblox- und TSMC CoWoS®-Technologien, die 5,5-fach größere Reticle-Größenpakete ermöglichen, sowie ein umfassendes IP-Portfolio mit dem niedrigsten Energieverbrauch bei den TSMC N2/N2P-Prozessen. Die Zusammenarbeit bietet vollständige IP-Lösungen für fortschrittliche Standards wie HBM4, 1.6T Ethernet, UCIe, PCIe 7.0 und UALink.
Die Partnerschaft erweitert die Fähigkeiten des 3DIC Compiler, unterstützt ultra-hochdichte Interconnects und steigert die Produktivität bei Multi-Die-Designs. Die Lösung integriert Multi-Physics-Analysen und Ansys-Simulationstechnologien für eine umfassende Analyse von Leistung, Thermik und Signalintegrität.
- Partnership enables advanced chip design capabilities for next-generation AI and HPC applications
- Expansion into TSMC's newest processes (A16, N2P, A14) strengthens market position
- Support for 5.5x reticle size packages enhances competitive advantage in 3D chip design
- Comprehensive IP portfolio offers multiple revenue streams across various standards
- None.
Insights
Synopsys-TSMC collaboration on angstrom-scale EDA flows and advanced IP enhances chip design capabilities for AI and high-performance computing.
The Synopsys-TSMC collaboration marks a significant technological milestone in semiconductor design, enabling the industry to push into the angstrom era of chip fabrication. The certification of Synopsys' digital and analog flows on TSMC's A16 and N2P processes provides designers with optimized toolsets for the most advanced nodes available, with early work already underway for the A14 process.
The backside routing capabilities certified for A16 represent a transformative approach to power distribution networks, fundamentally improving chip performance by utilizing silicon real estate more efficiently. This allows designers to overcome power delivery challenges that have traditionally performance scaling at advanced nodes.
Most impressive is the 3DIC Compiler support for TSMC's CoWoS technology enabling 5.5x reticle interposer sizes - a technical breakthrough that has already been validated in customer designs. This dramatically expands the interconnect density possible in heterogeneous integration, critical for AI accelerators that require massive parallel computation capabilities and memory bandwidth.
The comprehensive IP portfolio covering HBM4, 1.6T Ethernet, PCIe 7.0, and UALink provides essential building blocks that minimize integration risk for complex SoCs. The silicon-proven 224G PHY IP with demonstrated interoperability across optical and copper connections is particularly valuable for hyperscale data centers and AI training clusters where interconnect bandwidth is often the bottleneck.
Synopsys strengthens its EDA leadership position through TSMC partnership, extending its technology moat in high-growth AI chip design market.
This strategic collaboration with TSMC reinforces Synopsys' market position in the critical EDA and IP domains for semiconductor design. By securing certification for TSMC's most advanced nodes, Synopsys ensures it remains the go-to provider for companies designing cutting-edge AI and high-performance computing chips.
The article explicitly states multiple customers have already adopted Synopsys' Interface and Foundation IP solutions for TSMC's N2/N2P processes, confirming market traction. With "successful deployment of Synopsys IP in thousands of designs," the company has clearly established a substantial footprint in the semiconductor IP market.
Synopsys' expansion into comprehensive solutions for 3D multi-die designs positions the company advantageously in the fastest-growing segment of the semiconductor industry. As chipmakers increasingly move to chiplet architectures and heterogeneous integration to overcome traditional scaling limitations, Synopsys' certified tools for these advanced packaging technologies become mission-critical.
The breadth of silicon-proven IP offerings, including next-generation standards like HBM4, 1.6T Ethernet, PCIe 7.0, UCIe, and UALink, represents significant value for customers designing complex systems. The "first pass silicon success" mentioned delivers substantial cost savings and time-to-market advantages for customers, particularly valuable as initial design and mask costs at advanced nodes can reach hundreds of millions of dollars.
AI-Driven Digital and Analog Flows, Multi-Die Innovations, and Broad IP Portfolio Deliver Unmatched Performance, Power and Area Advantages
Highlights
- Digital and analog design flows on TSMC A16™ and N2P deliver optimized performance and rapid analog design migration, enabled by Synopsys.ai
- Early collaboration on TSMC A14 process underway for Synopsys EDA flows development
- Collaboration on 3Dblox and TSMC's CoWoS® technologies for 5.5x reticle size packages, speeds integration of 3D stacked dies in next-generation AI chips
- Broad portfolio of Synopsys Foundation and Interface IP provides the lowest power on TSMC's N2/N2P processes
- Industry's most complete IP solutions for leading-edge standards, including HBM4, 1.6T Ethernet, UCIe, PCIe 7.0, and UALink, enable high-bandwidth interfaces in data-intensive heterogeneous SoCs
Among the newest collaborations is availability of certified digital and analog flows on TSMC A16™ and N2P processes for design productivity and optimization, enabled by Synopsys.ai™, and initial development of EDA flows on TSMC's A14 process. Synopsys and TSMC are also working on the tool certification for the newly announced TSMC N3C technology, building on the available N3P design solutions. To further accelerate semiconductor design for ultra-high-density 3D stacking, the Synopsys 3DIC Compiler, certified by TSMC, supports 3Dblox and enables TSMC's CoWoS® technology with 5.5x-reticle interposer sizes. In addition, Synopsys provides complete, silicon-proven IP solutions on TSMC's advanced processes, enabling designers to rapidly integrate the necessary functionality into their next-generation designs with the lowest power and maximum performance.
"Synopsys and TSMC are helping the semiconductor industry speed up the pace of innovation for Angstrom-scale designs by providing mission-critical EDA and IP solutions optimized for the most advanced process technologies," said Sanjay Bali, Senior Vice President of Strategy and Product Management at Synopsys. "Together, we are delivering future-ready solutions that empower engineers to push the boundaries of technology, achieve their design goals, and bring their products to market faster."
"Achieving high quality-of-results and faster time to market for advanced SoC designs are the cornerstone of the long-standing collaboration between TSMC and Synopsys," said Lipen Yuan, Senior Director of Advanced Technology Business Development at TSMC. "Collaborating closely with our Open Innovation Platform® (OIP) design ecosystem partners like Synopsys is vital to enable our mutual customers with certified flows and high-quality IP that are essential to meet or exceed their design targets on TSMC's advanced processes."
Jumpstart Designs on TSMC's Angstrom-Scale Processes
Synopsys' analog and digital flows are certified on TSMC A16™ and N2P processes to deliver optimized quality of results and accelerate analog design migration. Certified backside routing capabilities support customers to take advantage of the TSMC A16™ process, improving power distribution and design performance. Pattern-based pin access methodology has been enhanced for TSMC N2P and A16™ nodes to deliver competitive area results. To further optimize TSMC N2P designs, Synopsys Fusion Compiler is enhanced with a frequency optimization (Fmax) engine and intelligent legalization technology to boost performance.
In addition, the ongoing collaboration on Synopsys EDA flows for TSMC's A14 process demonstrates Synopsys' continued commitment to enable Synopsys EDA flows for robust, high-performance designs.
Synopsys IC Validator™ signoff physical verification solution, including Design Rule Checks (DRC) and Layout Versus Schematic (LVS) checking, is certified for A16™ and N2P processes. In addition, IC Validator's high-capacity elastic architecture seamlessly scaled PERC rules to handle TSMC N2P electrostatic discharge (ESD) verification with improved turnaround time. Synopsys and TSMC also collaborated to certify IC Validator 3DIC solution for the 3Dblox standard.
Driving Successful Adoption of 3D Integration
Synopsys and TSMC are leading semiconductor innovation by enabling 3DIC Compiler to support TSMC's CoWoS® technology for unprecedented 5.5x reticle interposer sizes, which has been proven in customer designs. The collaboration helps mutual customers meet demanding compute performance requirements for next-generation HPC and AI chips using wafer-on-wafer and chip-on-wafer advanced packaging. For a seamless migration to 2.5D and 3D multi-die designs, Synopsys' 3DIC Compiler supports 3Dblox and provides a single environment for analysis-driven feasibility exploration, prototyping, and floorplanning. The platform offers high throughput routing automation to enable ultra-high-density interconnects and increased productivity. 3DIC Compiler integrates multi-physics analysis and signoff solutions combined with Ansys simulation technologies for power, thermal, and signal integrity analysis.
Reduce Risk with Industry's Broadest Interface and Foundation IP Portfolio
Adopted by multiple customers, Synopsys offers best-in-class Interface and Foundation IP solutions for TSMC's N2/N2P processes, enabling maximum performance with the lowest power for advanced HPC, edge, and automotive chips. With successful deployment of Synopsys IP in thousands of designs, Synopsys and TSMC continue to enable mutual customers to reduce integration risk while meeting stringent power, performance, and area targets. Synopsys' complete, silicon-proven IP solutions for leading standards such as 1.6T Ethernet, PCIe 7.0, UCIe, HBM4, USB4, DDR5, LPDDR6/5X/5, and MIPI, along with embedded memories, logic libraries and IOs, provide a low-risk path for first pass silicon success.
Additionally, Synopsys has expanded its IP solutions portfolio to include standards-based UALink and Ultra Ethernet IP, which is built on industry-leading PCIe and Ethernet IP. Synopsys' silicon-proven 224G PHY IP, a backbone of high-performance computing (HPC) systems, has demonstrated wide ecosystem interoperability including optical and copper connections, enabling an early start on advanced HPC and AI chips for upcoming standards.
Additional Resources
Synopsys is hosting several demonstrations at the TSMC Tech Symposium Forum today in
About Synopsys
Catalyzing the era of pervasive intelligence, Synopsys, Inc. (Nasdaq: SNPS) delivers trusted and comprehensive silicon to systems design solutions, from electronic design automation to silicon IP and system verification and validation. We partner closely with semiconductor and systems customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. Learn more at www.synopsys.com.
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Editorial Contact
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Synopsys, Inc.
Corp-pr@synopsys.com
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