Silvaco Announces Immediate Availability of Production Ready Mixel MIPI PHY IP, Strengthening its Comprehensive Silicon IP Offering

Silvaco (Nasdaq: SVCO) announced immediate global availability of Mixel MIPI PRO IP, a production-ready MIPI PHY and multi-standard SerDes portfolio.

Rhea-AI Summary

Silvaco (Nasdaq: SVCO) announced immediate global availability of Mixel MIPI PRO IP, a production-ready MIPI PHY and multi-standard SerDes portfolio. The IP is silicon-proven across 9 foundries and 12 process nodes (180nm–5nm), and includes patented MIPI D-PHY RX+ with 35% area and 50% leakage reductions.

The portfolio supports D-PHY v3.5, C-PHY v2.1, M-PHY v4.1, combo PHYs, and ASA Motion Link SerDes (up to 8.0Gbps/lane), targeting mobile, automotive, VR/AR, IoT, wearables, and sensors.

Positive

• Silicon-proven across 9 foundries and 12 nodes (180nm–5nm)
• Patented MIPI D-PHY RX+ reduces area by 35% and leakage by 50%
• Supports high speeds: D-PHY up to 6.5Gbps/lane, C-PHY up to 18.24Gbps, M-PHY up to 11.6Gbps
• Includes ASA Motion Link SerDes IP supporting up to 8.0Gbps/lane

Negative

• None.

Argus Mar 11 session

+0.30% close to close Open Argus

Details

News Market Reaction – SVCO

On Mar 11, the first trading day after this news, SVCO closed 0.30% above the previous close.

Data tracked by StockTitan Argus for the Mar 11 session.

Key Figures

Area reduction: 35% reduction Leakage power cut: 50% reduction Foundry coverage: 9 foundries +5 more

Area reduction

35% reduction

MIPI D-PHY RX+ patented implementation vs full Universal configuration

Leakage power cut

50% reduction

MIPI D-PHY RX+ implementation enabling full-speed production testing

Foundry coverage

9 foundries

Mixel IP silicon-proven across multiple manufacturing partners

Process nodes

12 nodes (180nm to 5nm)

Mixel IP silicon-proven from legacy to advanced nodes

MIPI D-PHY speed

6.5Gbps per lane

MIPI D-PHY v3.5 supporting 1–4 data lanes

MIPI C-PHY rate

8.0Gsps per trio

MIPI C-PHY v2.1 supporting 1–3 trios (18.24Gbps)

MIPI M-PHY speed

11.6Gbps

MIPI M-PHY v4.1 supporting HS-G1 to HS-G4

ASA Motion Link

8.0Gbps per lane

ASA Motion Link SerDes IP downstream TX/RX with NRZ signaling

Historical Context

5 past events · Latest: Feb 26

5 events

1. Feb 26

   Earnings call date

   24h Move

   -2.6%

   Set date and time for Q4 2025 earnings release and conference call.

2. Jan 05

   Investor conference

   24h Move

   +7.3%

   CEO fireside chat at Needham Growth Conference with webcast access.

3. Nov 20

   Automotive IP integration

   24h Move

   +3.5%

   Mixel MIPI IP integrated into indie automotive radar processors and MMICs.

4. Nov 12

   Q3 2025 earnings

   24h Move

   -8.3%

   Record revenue and bookings, high margins, but report of operating and net loss.

5. Nov 10

   Litigation settlement

   24h Move

   +1.6%

   Settlement resolving all prior Nangate litigation after appellate court reversal.

24h Move is the share-price change in the day after each event; other market factors may also have contributed.

Key Terms

serdes, lvds

2 terms

serdes technical

"and multi-standard SerDes IP including MIPI C-PHY/D-PHY combo IP"

SerDes (short for serializer/deserializer) is an electronic function that converts parallel streams of data into a single fast serial stream and then converts it back, like packing many lanes of traffic into one high-speed highway and unpacking them at the other end. Investors care because SerDes chips and blocks determine how quickly and efficiently devices, data centers and networks can move information; improvements or bottlenecks affect product performance, production costs, and demand across the semiconductor and communications supply chain.

lvds technical

"Mixel MIPI D-PHY/LVDS Combo: Dual-mode PHY supporting MIPI D-PHY and LVDS"

LVDS (low-voltage differential signaling) is an electrical standard for sending high-speed data between chips or devices using a pair of wires that carry opposite voltages to cancel noise. Think of it like a balanced two-lane road where opposite traffic keeps the path stable and fast. Investors care because LVDS affects product performance, power use, and compatibility in markets like chips, displays, and networking, influencing manufacturers’ costs, design choices, and competitive edge.

AI-generated analysis. How Rhea-AI works. Not financial advice.

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SANTA CLARA, Calif., March 10, 2026 (GLOBE NEWSWIRE) -- Silvaco Group, Inc. (Nasdaq: SVCO) (“Silvaco”), a provider of AI enabled TCAD and EDA solutions, and SIP solutions that enable semiconductor design and digital twin modeling through AI software and innovation, announces the immediate availability of Mixel^TM, MIPI^® “Production Ready Offerings,” or Mixel MIPI “PRO IP”. This announcement reinforces Silvaco’s commitment to providing silicon-proven, high-performance connectivity solutions with outstanding customer service, building on its reputation for "Mixed-Signal Excellence."

The Mixel MIPI IP portfolio includes MIPI PHY (MIPI D-PHY^TM, MIPI C-PHY^TM, and MIPI M-PHY^®) and multi-standard SerDes IP including MIPI C-PHY/D-PHY combo IP and LVDS/D-PHY combo IP. Mixel also announced support for the Automotive SerDes Alliance (ASA) Motion Link IP last year. This expands Silvaco’s semiconductor IP offering in mobile and mobile-adjacent markets such as automotive, virtual reality (VR), augmented reality (AR), Internet of Things (IoT), wearables, and sensors.

Mixel’s MIPI PHY IP are silicon-proven in multiple MIPI-compliant configurations including proprietary topologies such as MIPI D-PHY RX⁺. This patented implementation allows for full-speed production testing without requiring a full D-PHY Universal configuration, resulting in a substantial reduction of 35% in area and 50% reduction in leakage power. This solution was first announced in 2015 and is in production at many of the world’s largest semiconductor and system companies in mission-critical applications.

Moving beyond MIPI, Mixel was the first pure-play silicon IP provider to announce availability of the ASA Motion Link SerDes IP in 2025. The Automotive SerDes Alliance was formed to standardize long reach, asymmetric SerDes connectivity for automotive applications.

The Mixel IP solutions are silicon-proven in 9 different foundries and 12 different nodes, from 180nm down to 5nm. The Mixel mixed-signal IP portfolio includes:

MIPI PHY

• MIPI D-PHY IP v3.5 (backwards compatible). Supports 1–4 data lanes, up to 6.5Gbps/lane. Supports MIPI CSI-2 and MIPI DSI/DSI-2. Available as TX, RX, TX+, RX+, and Universal implementations.
• MIPI C-PHY IP v2.1 (backwards compatible). Supports 1-3 trios (lanes), up to 8.0Gsps/trio (18.24Gbps). Supports MIPI CSI-2 and MIPI DSI/DSI-2. Available as TX, RX, TX+, RX+, and Universal implementations.
• MIPI M-PHY IP v4.1 (backwards compatible). Supports HS-G1 to HS-G4 (up to 11.6Gbps). Supports MIPI UniPro and JEDEC Universal Flash Storage (UFS) standard.
  
  

Multi-standard SerDes

• MIPI C-PHY/D-PHY Combo IP: Dual-mode PHY supporting MIPI C-PHY v2.1 and MIPI D-PHY v3.5. Supports 4 lanes/3 trios, up to 8.0Gsps/trio and 6.5Gbps/lane. Supports MIPI CSI-2 and MIPI DSI/DSI-2. Available as TX, RX, TX+, RX+, and Universal implementations.
• Mixel MIPI D-PHY/LVDS Combo: Dual-mode PHY supporting MIPI D-PHY and LVDS compatible with TIA/EIA-644 standard. Available as Transmitter (TX) and Receiver (RX).
  
  

Automotive SerDes Alliance

• ASA Motion Link SerDes IP: supports v2.1 and supports transmitting (TX) and receiving (RX) downstream speeds of up to 8.0Gbps/lane with NRZ signaling (Speed Grade 3).
  
  

The availability of the Mixel MIPI IP portfolio strengthens Silvaco’s broader IP offerings with high-performance interface solutions. By combining Mixel’s mixed-signal IP leadership with Silvaco’s extensive IP ecosystem, Silvaco is advancing a larger strategy to lead the semiconductor IP market by expanding IP coverage at the most advanced process nodes and supporting a wider range of high-growth applications, while maintaining the same focus on quality, reliability, and customer success.

“I am excited to announce the immediate global availability of our world-class production ready MIPI solutions,” said Andy Wright, Senior Vice President and General Manager of the Semiconductor IP Business Unit at Silvaco. “Mixel’s 27-year history of first-time silicon success, coupled with Silvaco’s global reach, provides our partners with best in class, proven solutions that solve their biggest interconnect challenges.”

For more information about Mixel’s MIPI Production Ready Offerings (MIPI PRO IP), visit Silvaco’s website or contact us here.

About Silvaco Group, Inc.
Silvaco is a provider of AI-enabled TCAD and EDA solutions, and SIP solutions that enable semiconductor design and digital twin modeling through AI software and innovation. Silvaco’s solutions are used for semiconductor and photonics processes, devices, and systems development across display, power devices, automotive, memory, high performance compute, foundries, photonics, internet of things, and 5G/6G mobile markets for complex SoC design. Silvaco is headquartered in Santa Clara, California, and has a global presence with offices located in North America, Europe, Brazil, China, Japan, Korea, Singapore, and Taiwan. Learn more at silvaco.com.

Mixel, a Silvaco company, is a provider of mixed-signal IPs and offers a wide portfolio of high-performance mixed-signal connectivity IP solutions. Mixel’s mixed-signal portfolio includes PHYs and SerDes, such as MIPI D-PHY, MIPI M-PHY, MIPI C-PHY, Automotive SerDes Alliance (ASA) Motion Link SerDes, LVDS, and many dual mode PHY supporting multiple standards. Mixel was founded in 1998 and is headquartered in San Jose, CA, with global operation to support a worldwide customer base. Learn more at mixel.com.

MIPI^® and MIPI M-PHY^® are registered trademarks owned by MIPI Alliance. MIPI C-PHY^TM and MIPI D-PHY^TM are trademarks of MIPI Alliance.

Contacts
Media Relations:
press@silvaco.com

Investor Relations:
Greg McNiff, investors@silvaco.com

FAQ

AI-generated questions and answers. How Rhea-AI works. Not financial advice.

What Mixel MIPI IP did Silvaco (SVCO) make available on March 10, 2026?

Silvaco made the Mixel MIPI PRO IP portfolio immediately available for production use. According to the company, the release includes MIPI D-PHY v3.5, C-PHY v2.1, M-PHY v4.1, combo PHYs, and ASA Motion Link SerDes IP for production deployment.

How does the MIPI D-PHY RX+ in Silvaco's Mixel IP affect chip design?

MIPI D-PHY RX+ reduces silicon area and leakage for production testing and deployment. According to the company, the patented RX+ topology yields a 35% area reduction and 50% lower leakage, enabling smaller, lower-power interface implementations.

Which process nodes and foundries support Silvaco's Mixel MIPI IP (SVCO)?

The Mixel MIPI IP is silicon-proven across multiple foundries and nodes. According to the company, the portfolio is validated in 9 different foundries and across 12 process nodes ranging from 180nm down to 5nm.

What performance limits do Silvaco's Mixel C-PHY, D-PHY, and M-PHY IP claim?

The IP supports high-speed MIPI standards with explicit lane/trio rates. According to the company, D-PHY supports up to 6.5Gbps/lane, C-PHY up to 8.0Gsps/trio (18.24Gbps), and M-PHY up to 11.6Gbps depending on speed grade.

How does Silvaco position Mixel MIPI PRO IP for automotive applications under SVCO?

Silvaco highlights automotive-ready SerDes support and standards alignment for long-reach links. According to the company, Mixel supports the ASA Motion Link SerDes IP and targets automotive connectivity needs with Motion Link speeds up to 8.0Gbps/lane.