Silvaco Announces Immediate Availability of Mixel MIPI C-PHY/D-PHY Combo IP on TSMC N2P Process

(Neutral)

(Very Positive)

Rhea-AI Summary

Silvaco (Nasdaq: SVCO) announced immediate availability of the Mixel MIPI C-PHY/D-PHY Combo Universal IP on TSMC’s N2P process. The IP supports MIPI C-PHY v2.1 and MIPI D-PHY v3.6 with embedded clock mode, targeting low-power, small-form-factor applications like AR glasses.

It delivers up to 3.0 Gbps per lane in D-PHY mode and 3.0 Gsps per trio in C-PHY mode, achieving similar throughput with about 25% fewer wires than standard forwarded-clock combos, and is available now on TSMC N2P.

News Market Reaction – SVCO

-2.01%

-2.01% Session close to close

In the May 19 session, SVCO declined 2.01%, reflecting a moderate negative market reaction.

Data tracked by StockTitan Argus on the day of publication.

Market Context

This announcement highlights Silvaco’s expansion of its SIP portfolio, with Mixel MIPI C-PHY/D-PHY c...

Analysis

This announcement highlights Silvaco’s expansion of its SIP portfolio, with Mixel MIPI C-PHY/D-PHY combo IP on TSMC’s N2P process supporting up to 3.0 Gbps per lane and achieving equivalent rates of 6.84 Gbps/trio with 25% fewer wires. Historically, the company paired such technology progress with partnerships and solid Q1 2026 growth of $17.8M revenue. Investors may watch future updates on IP adoption, use of the $50,000,000 shelf and $35.0 million ATM, and how these balance growth with dilution risk.

Key Figures

MIPI D-PHY spec: v3.6 MIPI C-PHY spec: v2.1 D-PHY data rate: 3.0 Gbps per lane +5 more

8 metrics

MIPI D-PHY spec v3.6 Supported by Mixel MIPI D-PHY IP on TSMC N2P

MIPI C-PHY spec v2.1 Supported by Mixel MIPI C-PHY IP

D-PHY data rate 3.0 Gbps per lane Speed in D-PHY mode over two wires

C-PHY symbol rate 3.0 Gsps per trio MIPI C-PHY v2.1 specification on N2P

C-PHY equivalent rate 6.84 Gbps/trio Equivalent data rate for MIPI C-PHY v2.1

Wire reduction 25% fewer wires Throughput vs standard MIPI C-PHY/D-PHY with forwarded-clock

Silicon-proven nodes 10 TSMC process nodes MIPI PHY IP silicon-proven including N6 and N5

First combo demo 2016 First silicon-proven MIPI C-PHY/D-PHY combo IP demonstration

Historical Context

5 past events · Latest: May 07 (Positive)

Pattern 5 events

Date	Event	Sentiment	24h Move	Catalyst
May 07	Q1 2026 earnings	Positive	-4.7%	Reported 26% revenue growth and margin gains with narrowed operating loss.
May 04	Investor conferences	Neutral	+4.0%	Announced CEO and CFO participation in May technology investor conferences.
Apr 23	Earnings call date	Neutral	+9.8%	Set timing for Q1 2026 results release and conference call details.
Apr 20	ITRI partnership	Positive	+3.2%	Partnered with ITRI to deploy SmartSpice at an IC design incubator.
Mar 30	APEC partnership	Positive	+2.9%	Expanded APEC partnership to accelerate silicon carbide power device development.

24h Move is the share-price change in the day after each event; other market factors may also have contributed.

Pattern Detected

Recent news has usually seen positive price alignment, with one notable divergence on strong Q1 2026 earnings where shares fell despite upbeat metrics.

Recent Company History

Over the past few months, Silvaco has reported strong Q1 2026 results with revenue of $17.8M (+26% YoY) and improving margins, while also expanding at-the-market capacity and executing a restructuring plan. Strategically, the company pursued partnerships with ITRI and APEC to deepen adoption of its TCAD and circuit simulation tools. It also increased investor outreach via May 2026 conferences. Today’s product-focused IP announcement continues that theme of broadening technology offerings on advanced nodes.

Key Terms

mipi c-phy, mipi d-phy, embedded clock mode, physical layer, +2 more

6 terms

mipi c-phy technical

"Mixel™ MIPI® C-PHY™/D-PHY™ Combo Universal IP on TSMC’s industry-leading N2P process."

MIPI C-PHY is a standardized physical connection used to carry high-speed camera and sensor data inside phones, tablets, cars and other electronics; think of it as a different kind of wiring that lets more information travel faster and with less power than older links. Investors care because choice of interface affects product performance, battery life, manufacturing cost and compatibility across suppliers, which in turn can influence component demand, margins and time to market.

mipi d-phy technical

"The MIPI C-PHY IP supports the v2.1 specification, and the MIPI D-PHY IP supports the v3.6 specification."

MIPI D-PHY is a widely used hardware interface standard that defines the electrical signals and timing rules for connecting cameras, displays and other peripherals to processors in mobile and embedded devices. For investors, broad adoption matters because it makes components more interchangeable and lower-cost, shapes product performance and power use, and influences which suppliers win design contracts—think of it as a common plug and wiring spec that eases manufacturing and upgrades.

embedded clock mode technical

"this IP supports MIPI D-PHY with embedded clock mode (ECM), a new mode first released in the MIPI D-PHY v3.5"

Embedded clock mode is a way electronic systems carry timing information inside the same signal that carries data, rather than sending a separate clock signal alongside it. For investors, this design choice can simplify circuitry, lower parts count and power use, and affect product reliability and compatibility—properties that influence manufacturing cost, supply-chain risk and the competitive appeal of devices, much like embedding a hidden timestamp inside a video stream instead of running a separate stopwatch.

physical layer technical

"The Mixel MIPI C-PHY/D-PHY Combo Universal IP is a physical layer specifically optimized for low power"

The physical layer is the part of a communications system that handles the actual transmission of raw digital signals over cables, fiber, radio waves or other media. Think of it as the pipes and wiring that carry data — it doesn't interpret the content, it only moves the bits. Investors watch it because changes in capacity, reliability, technology upgrades or regulation at this level affect network performance, costs and capital spending for tech and telecom businesses.

emi technical

"designed for use cases where power efficiency, minimal area, low EMI, and low heat dissipation are critical"

An EMI is a UK tax-advantaged employee share option plan that lets a company grant executives and staff the right to buy shares at a preset price after a vesting period. It matters to investors because it aligns employees’ incentives with company performance—like giving key workers a stake in the business—while potentially diluting existing shareholders and changing future earnings per share when options are exercised.

augmented reality technical

"Such applications include augmented reality (AR) glasses and wearables."

Augmented reality is technology that layers computer-generated images, information or sounds onto your view of the real world through devices like phones, tablets or smart glasses — like seeing navigation arrows or product labels projected onto what you’re looking at. It matters to investors because it creates new ways to sell hardware, software, services and ads, can change customer engagement and recurring revenue models, and carries adoption and privacy risks that affect company value.

AI-generated analysis. How Rhea-AI works. Not financial advice.

See more from StockTitan in Google Search and AI answers. Adds StockTitan as a preferred source · opens Google

Add on Google

05/19/2026 - 09:00 AM

The Mixel combo IP is the industry’s first to support MIPI D-PHY v3.6 with embedded clock mode

SAN JOSE, Calif., May 19, 2026 (GLOBE NEWSWIRE) -- Silvaco Group, Inc. (Nasdaq: SVCO) (“Silvaco”), a provider of AI-enabled TCAD and EDA solutions, and SIP solutions that enable semiconductor design and digital twin modeling through AI software and innovation, announces the immediate availability of Mixel™ MIPI^® C-PHY™/D-PHY™ Combo Universal IP on TSMC’s industry-leading N2P process. The MIPI C-PHY IP supports the v2.1 specification, and the MIPI D-PHY IP supports the v3.6 specification.

The Mixel MIPI C-PHY/D-PHY Combo Universal IP is a physical layer specifically optimized for low power, low leakage, and minimal area. In an industry first, this IP supports MIPI D-PHY with embedded clock mode (ECM), a new mode first released in the MIPI D-PHY v3.5 specification and carried forward in v3.6. The Mixel IP supports speeds up to 3.0 Gbps per lane in D-PHY mode over two wires, compared to a traditional MIPI D-PHY interface requiring a minimum of four wires with a forwarded-clock mode. The combo IP also supports the MIPI C-PHY v2.1 specification at 3.0 Gsps per trio, an equivalent data rate of 6.84 Gbps/trio. As a universal IP, it is the superset configuration that includes a high-speed transmitter and receiver supporting full-speed loopback.

This IP was specifically designed for use cases where power efficiency, minimal area, low EMI, and low heat dissipation are critical—without compromising performance. Such applications include augmented reality (AR) glasses and wearables. By leveraging the latest features available in the MIPI specification, the Mixel MIPI C-PHY/D-PHY ECM combo achieves the same throughput with 25% fewer wires compared to a standard MIPI C-PHY/D-PHY combo with a forwarded-clock D-PHY IP. The reduced wire count is beneficial for use cases with extreme form factor constraints such as AR glasses where all wires need to fit inside a lens frame.

“Mixel, now part of Silvaco, has long been a valued contributing member of the MIPI Alliance,” said Hezi Saar, chair of MIPI Alliance. “It is great to see these two companies combining their strengths to deliver MIPI C-PHY and D-PHY solutions on TSMC’s advanced N2P process.”

Mixel was the first IP provider to demonstrate silicon-proven MIPI C-PHY with its MIPI C-PHY/D-PHY combo IP in 2016. Mixel’s MIPI PHY IP has been silicon-proven in 10 different TSMC process nodes including N6 and N5.

“We are excited to announce immediate availability of our next-generation MIPI C-PHY/D-PHY IP on TSMC’s N2P process, the advanced Nanosheet technology delivering industry-leading performance and energy efficiency,” said Andy Wright, SVP and GM of Silvaco Semiconductor IP. “This demonstrates our ongoing commitment to expand our portfolio to the leading-edge processes, providing customers with high-performance, reliable solutions for next-generation applications.”

Availability:

Mixel MIPI C-PHY/D-PHY Combo IP is available now on TSMC N2P process. For more information on Mixel’s IP portfolio, please visit https://mixel.com/ip-cores/.

About Silvaco Group, Inc.
Silvaco is a provider of AI-driven TCAD and EDA solutions, and SIP solutions that enable semiconductor design and digital twin modeling through AI software and innovation. Silvaco’s solutions are used for semiconductor and photonics processes, devices, and systems development across display, power devices, automotive, memory, high performance compute, foundries, photonics, internet of things, and 5G/6G mobile markets for complex SoC design. Silvaco is headquartered in Santa Clara, California, and has a global presence with offices located in North America, Europe, Brazil, China, Japan, Korea, Singapore, and Taiwan. Learn more at silvaco.com.

About Mixel:

Mixel, a Silvaco company, is a provider of mixed-signal IPs and offers a wide portfolio of high-performance mixed-signal connectivity IP solutions. Mixel’s mixed-signal portfolio includes PHYs and SerDes, such as MIPI D-PHY, MIPI M-PHY, MIPI C-PHY, Automotive SerDes Alliance (ASA) Motion Link SerDes, LVDS, and many dual mode PHY supporting multiple standards. Mixel was founded in 1998 and is headquartered in San Jose, CA, with global operation to support a worldwide customer base. Learn more at mixel.com.

About MIPI Alliance:

MIPI Alliance (MIPI) develops standardized wired interface specifications for mobile and other connected ecosystems. Founded in 2003, the organization has over 375 member companies worldwide and more than 15 active working groups delivering specifications within the extended mobile ecosystem. Members of the organization include handset manufacturers, device OEMs, software providers, semiconductor companies, application processor developers, IP tool providers, automotive OEMs and Tier 1 suppliers, and test and test equipment companies, as well as camera, display, tablet and laptop manufacturers. For more information, please visit www.mipi.org.

MIPI^® and M-PHY^® are registered trademarks owned by MIPI Alliance. C-PHY™ and D-PHY™ are trademarks of MIPI Alliance.

Investor Relations:
Greg McNiff
investors@silvaco.com

Media Relations:
press@silvaco.com

FAQ

What did Silvaco (SVCO) announce on May 19, 2026 about Mixel MIPI C-PHY/D-PHY IP?

Silvaco announced immediate availability of the Mixel MIPI C-PHY/D-PHY Combo Universal IP on TSMC’s N2P process. According to Silvaco, the IP targets low power, low leakage, and minimal area for advanced applications like AR glasses and wearables.

What MIPI specifications does Silvaco’s Mixel C-PHY/D-PHY Combo IP on TSMC N2P support?

The combo IP supports MIPI C-PHY v2.1 and MIPI D-PHY v3.6 with embedded clock mode. According to Silvaco, the D-PHY runs up to 3.0 Gbps per lane and C-PHY up to 3.0 Gsps per trio, enabling high-throughput interfaces.

Why is Silvaco’s Mixel MIPI D-PHY v3.6 IP on TSMC N2P described as an industry first?

It is described as the industry’s first MIPI D-PHY v3.6 IP supporting embedded clock mode. According to Silvaco, embedded clock mode was introduced in D-PHY v3.5, and this IP integrates it while optimizing for low power and minimal area on TSMC N2P.

How does the Mixel MIPI C-PHY/D-PHY Combo IP reduce wire count for AR glasses applications?

The combo IP achieves the same throughput using about 25% fewer wires than a standard forwarded-clock combo. According to Silvaco, this reduced wire count helps in extreme form-factor designs like AR glasses, where all wires must fit inside compact lens frames.

What performance does Silvaco’s Mixel MIPI C-PHY/D-PHY IP on TSMC N2P deliver per lane or trio?

The IP delivers up to 3.0 Gbps per lane in D-PHY mode and 3.0 Gsps per trio in C-PHY mode. According to Silvaco, C-PHY’s 3.0 Gsps translates to an effective data rate of 6.84 Gbps per trio.

Which applications does Silvaco target with its Mixel MIPI C-PHY/D-PHY Combo IP on TSMC N2P?

The IP targets applications needing high throughput with low power, low EMI, and small area, such as AR glasses and wearables. According to Silvaco, it is designed for use cases where heat dissipation and extreme form-factor constraints are critical.