VisionWave and Boca Jom, Ltd. Near Completion of AstraDRC™ POC, a Patented Automatic DRC Violation Correction Platform for Advanced AI Microchips
Rhea-AI Summary
VisionWave (NASDAQ:VWAV) and joint-venture partner Boca Jom, Ltd. are completing a proof-of-concept release of AstraDRC™, a patented automated DRC-violation correction platform for advanced IC designs. The POC is scheduled for demonstration and evaluation by a major AI microchip semiconductor corporation.
AstraDRC™ uses the qSpeed™ accelerator to process multi-billion-device designs, aims to preserve electrical intent while correcting violations, and introduces layout compaction to improve silicon utilization and routing efficiency for advanced nodes including 5nm and 3nm.
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News Market Reaction
On the day this news was published, VWAV declined 6.37%, reflecting a notable negative market reaction.
Data tracked by StockTitan Argus on the day of publication.
Key Figures
Market Reality Check
Peers on Argus
VWAV was down 9.56% pre-announcement while momentum data flagged only DPRO moving up. Other listed peers showed mixed, modest moves, pointing to stock-specific factors rather than a broad sector shift.
Previous AI Reports
| Date | Event | Sentiment | Move | Catalyst |
|---|---|---|---|---|
| Dec 23 | AI patent issuance | Positive | +10.1% | USPTO issued new RF imaging and AI patent expanding core platform protection. |
| Oct 30 | AI infra partnership | Positive | -10.7% | Partnership to add AI infrastructure integration with deployment roadmap through 2027. |
| Aug 12 | AI spotlight report | Positive | +10.7% | Coverage highlighting VWAV as pure-play AI defense with funding and market focus. |
| Jul 28 | AI financing deal | Positive | +368.1% | $50M equity line plus $5M convertible note to fund AI defense platform. |
| Jul 22 | Nasdaq listing | Positive | -1.9% | Public market debut with AI-driven defense platform and defined growth priorities. |
AI-tagged announcements for VWAV have produced large but mixed reactions, with both strong rallies and sharp selloffs around IP, financing, and platform news.
Over the past months, VWAV’s key developments have centered on AI-driven defense and infrastructure. Earlier AI-tagged milestones include a Nasdaq debut on Jul 22, 2025, a $50 million equity line on Jul 28, 2025, and a spotlight report positioning VWAV as a pure-play AI defense stock on Aug 12, 2025. Later, the company announced an AI infrastructure integration partnership and a new RF/AI patent. Today’s AstraDRC™ AI design-automation POC continues this pattern of expanding AI-focused capabilities.
Historical Comparison
Across 5 prior AI-tagged releases, VWAV’s average 24h move was about 80.27%, underscoring historically high sensitivity to AI-related narratives and financings.
AI-tagged history shows VWAV progressing from Nasdaq listing and major AI financing, through strategic AI partnerships and a new RF/AI patent, toward increasingly specialized platforms like today’s AstraDRC™ design-automation POC.
Market Pulse Summary
The stock moved -6.4% in the session following this news. A negative reaction despite upbeat AI product positioning would fit VWAV’s volatile pattern around AI news, where average moves have reached 80.27%. The AstraDRC™ POC targets advanced-node AI microchips, but the company’s disclosures on financing structures and past dilution mechanisms in regulatory filings highlight ongoing capital and governance risks that could reinforce downside pressure after strong prior rallies.
Key Terms
design rule check technical
finfet technical
rf technical
swap technical
AI-generated analysis. Not financial advice.
POC scheduled for demo and evaluation with an AI microchip semiconductor corporation; qSpeed acceleration enables scalable processing of multi-billion-device designs
WEST HOLLYWOOD, Calif., Feb. 02, 2026 (GLOBE NEWSWIRE) -- VisionWave today announced that, together with its joint-venture partner Boca Jom, Ltd., it is completing a proof-of-concept (POC) release of AstraDRC™, a patented, automated Integrated Circuit (IC) Design Rule Check (DRC) violation correction technology designed to accelerate and streamline advanced semiconductor design. The POC is scheduled for demonstration and evaluation by a major AI microchips semiconductor corporation.
AstraDRC™ automatically identifies and corrects IC design rule violations while preserving electrical intent and layout integrity—replacing time-consuming, repetitive manual and semi-manual correction loops that can extend tape-out schedules. By reducing the time spent on iterative DRC closure, AstraDRC™ is designed to help teams compress overall design cycle timelines—with the goal of potentially saving months or more on complex programs, particularly for large-scale AI chips.
In addition to automation, AstraDRC™ introduces layout compaction capabilities as part of its correction methodology—seeking to reduce layout footprint, improve routing efficiency, and support higher silicon utilization. For semiconductor organizations, improved utilization can translate into higher yield per wafer and stronger economics at scale, especially when manufacturing advanced-node devices.
To support today’s AI-class microchips—often containing billions of devices and extreme rule complexity—VisionWave and Boca Jom, Ltd. leverage the qSpeed™ core accelerator engine, enabling AstraDRC™ to process very large and highly complex designs in practical runtimes. This scalable compute foundation is intended to help semiconductor corporations move faster from design to manufacture, improving productivity without compromising quality.
“AstraDRC™ represents a step-change in how advanced-node designs can reach DRC closure,” said Dr. Danny Rittman, CTO at VisionWave. “By combining patented automatic correction with qSpeed acceleration, we’re targeting the largest and most complex AI designs—helping shorten iterative closure loops, improve layout efficiency, and support faster time-to-market with higher confidence.”
Built for the Full Spectrum of Advanced IC Design
AstraDRC™ is being developed to support a broad range of design styles and manufacturing requirements, including:
- Advanced nodes: targeting deep-nanometer scaling including 5nm, 3nm, and below
- Design domains: Digital, Analog, RF, and AMS (Analog/Mixed-Signal)
- Device/layout paradigms: FinFET, GAAFET, and multi-patterning-aware layout requirements
- Design structures: flat blocks and fully hierarchical integrated circuits
During automatic correction, AstraDRC™ is designed to maintain electrical connectivity, honor and improve applicable layout constraints, preserve critical silicon resources, and adhere to DFM (Design for Manufacturing) requirements—supporting manufacturable, scalable outcomes rather than rule-only closure.
VisionWave also noted that AstraDRC™ aligns with the company’s longer-term semiconductor strategy, which includes the intent to design its own application-specific AI microchips for select defense and civil use cases. By coupling specialized silicon with its software platforms, VisionWave aims to deliver a hybrid hardware–software AI stack optimized for performance, power efficiency, and mission-specific reliability—enabling differentiated capabilities in edge and deployed environments where SWaP (Size, Weight, and Power) constraints, latency, and operational robustness are critical.
VisionWave expects AstraDRC™ to serve as the foundation of a broader roadmap of automation-first EDA technologies aimed at significantly improving semiconductor design productivity, enabling faster iteration cycles and contributing to the continued advancement of global computing and AI infrastructure.
About VisionWave Holdings, Inc.
VisionWave Holdings, Inc. (Nasdaq: VWAV) is focused on advanced sensing, autonomy, and AI-driven systems for defense and security applications. VisionWave develops proprietary radio-frequency sensing, computational acceleration, and decision-support technologies intended to enhance situational awareness and time-critical response across complex operational environments.
CAUTIONARY STATEMENT REGARDING FORWARD-LOOKING STATEMENTS
This press release contains forward-looking statements within the meaning of the federal securities laws. These include statements regarding the anticipated completion and demonstration of the AstraDRC™ proof-of-concept (POC), its potential benefits, capabilities, performance, processing scalability, timeline compression, layout improvements, economic advantages, support for advanced nodes and design types, and VisionWave’s longer-term strategy to design its own AI microchips and develop a broader roadmap of EDA technologies.
These statements are based on current expectations, assumptions, and projections about the company’s business, the semiconductor industry, and other future events, and are subject to risks, uncertainties, and other factors that could cause actual results, performance, achievements, timelines, or outcomes to differ materially from those expressed or implied.
Forward-looking statements can be identified by words such as “near completion,” “completing,” “scheduled,” “designed to,” “intended to,” “expects,” “aims,” “represents,” “targeting,” “helping,” “enabling,” “potential,” “potentially,” “may,” “could,” “will,” “seek,” and similar expressions. These statements speak only as of the date of this press release, and the company undertakes no obligation to update or revise any forward-looking statements, whether as a result of new information, future events, or otherwise, except as may be required by applicable law.
Important factors that could cause actual results to differ materially include, but are not limited to: risks that the POC may not be completed on the anticipated timeline or at all, or may not perform as expected during demonstration or evaluation; risks that the major AI microchip semiconductor corporation (or any other party) may not proceed with evaluation, provide positive feedback, enter into any agreement, or ultimately adopt or license the technology; technical, engineering, or scalability challenges in processing multi-billion-device designs or achieving practical runtimes with qSpeed™; failure to preserve electrical intent, layout integrity, connectivity, constraints, DFM requirements, or manufacturability during automated corrections; delays or difficulties in achieving DRC closure, compaction benefits, higher silicon utilization, yield improvements, or economic advantages at commercial scale; uncertainties in advanced-node semiconductor development (including 5nm, 3nm, and below), including evolving process technologies (FinFET, GAAFET, multi-patterning), design complexity, and manufacturing variability; competitive pressures in the EDA and semiconductor markets; reliance on the qSpeed™ accelerator and potential limitations in its performance or applicability; risks related to joint-venture arrangements with Boca Jom, Ltd., including alignment of interests, execution, or IP matters; challenges in developing or commercializing application-specific AI microchips for defense or civil use cases, including SWaP constraints, reliability requirements, or market acceptance; regulatory, export control, intellectual property, or geopolitical risks affecting the semiconductor industry; and general economic, market, or industry conditions that could impact demand for AI microchips or EDA tools. These and other risks are described in more detail in the company’s other communications and should be carefully considered by readers.
Investors, potential partners, and others are cautioned not to place undue reliance on these forward-looking statements.
Contacts:
VWAV - Investor Contact:
investors@vwav.inc
Website:
https://www.vwav.inc
FAQ
What is AstraDRC™ from VisionWave (VWAV) and what problem does it solve?
How does qSpeed™ acceleration help AstraDRC™ handle large AI microchip designs for VWAV?
Which process nodes and design domains does AstraDRC™ target for Volkswagen (VWAV)?
What benefits does AstraDRC™ claim for semiconductor yield and layout efficiency for VWAV shareholders?
What is the current commercialization milestone for AstraDRC™ announced by VisionWave (VWAV)?
