Marvell Demonstrates Industry's Leading 2nm Silicon for Accelerated Infrastructure
Rhea-AI Summary
Marvell Technology (NASDAQ: MRVL) has unveiled its first 2nm silicon IP platform for next-generation AI and cloud infrastructure, produced on TSMC's 2nm process. The platform includes advanced features such as high-speed 3D I/O for vertically stacking die inside chiplets, with bi-directional I/O operating at speeds up to 6.4 Gbits/second.
The company's platform strategy focuses on developing semiconductor IP components including SerDes, die-to-die interconnects, silicon photonics, and compute fabric interfaces. These serve as building blocks for custom AI accelerators, CPUs, and networking solutions.
Notable market projections indicate custom silicon is expected to represent approximately 25% of the accelerated compute market by 2028, with a 45% annual TAM growth. The new bi-directional I/O technology enables up to 2x bandwidth increase or 50% reduction in connections, particularly beneficial as an estimated 30% of advanced node processors are expected to utilize chiplet designs.
Positive
- First-to-market with 2nm silicon platform demonstration
- New bi-directional I/O technology doubles bandwidth potential
- Strong market growth projection of 45% annual TAM
- Expected 25% market share in accelerated compute by 2028
Negative
- High dependence on TSMC for manufacturing process
- Complex chiplet design requirements for advanced node processors
News Market Reaction
On the day this news was published, MRVL declined 6.52%, reflecting a notable negative market reaction.
Data tracked by StockTitan Argus on the day of publication.
- The Marvell® 2nm platform will enable hyperscalers to dramatically boost the performance and efficiency of their infrastructure to meet the performance and efficiency demands of the AI era.
- Built on TSMC's 2nm process, the silicon is a critical part of the Marvell platform for developing next-generation custom AI accelerators, CPUs, and networking.
- The silicon IP includes high-speed 3D I/O for vertically stacking die inside chiplets.
Given a projected
A Building Block Approach
The Marvell platform strategy centers around developing a comprehensive portfolio of semiconductor IP—including electrical and optical serializer/deserializers (SerDes), die-to-die interconnects for 2D and 3D devices, advanced packaging technologies, silicon photonics, custom high-bandwidth memory (HBM) compute architecture, on-chip static random-access memory (SRAM), system-on-chip (SoC) fabrics, and compute fabric interfaces such as PCIe Gen 7—that serve as building blocks for developing custom AI accelerators, CPUs, optical DSPs, high-performance switches and other technologies.
Advanced Technology Leadership
Starting with the launch of the industry's leading 5nm data infrastructure silicon platform in 2020, Marvell has been at the forefront of developing products produced on advanced technology nodes to market. Marvell announced the industry's leading 3nm platform in 2022, with first silicon produced in 2023 and multiple industry standard and custom silicon products now shipping and in development.
"The platform approach enables us to accelerate the development of market-leading high-speed SerDes and other critical technologies on the latest process manufacturing nodes, which in turn enables Marvell and its customers to accelerate the development of XPUs and other accelerated infrastructure technologies," said Sandeep Bharathi, chief development officer at Marvell. "Our longstanding collaboration with TSMC plays a pivotal role in helping Marvell develop complex silicon solutions with industry-leading performance, transistor density and efficiency."
New on the Marvell 2nm Platform
Additionally, Marvell delivered a 3D simultaneous bi-directional I/O operating at speeds up to 6.4 Gbits/second for connecting vertically stacked die inside of chiplets. Today, the I/O pathways connecting stacks of die are typically unidirectional. Shifting to a bi-directional I/O gives designers the ability to increase bandwidth by up to two times and/or reduce the number of connections by
3D simultaneous bi-directional I/O will also give chip designers greater flexibility in design. Today's most advanced chips exceed the size of the reticle, or photomask, for outlining transistor patterns onto silicon. To increase transistor count, an estimated
"TSMC is pleased to collaborate with Marvell on the development of its 2nm platform and the delivery of its first silicon," said Dr. Kevin Zhang, senior vice president of business development and global sales, and deputy co-chief operating officer at TSMC. "We look forward to our continued collaboration with Marvell to utilize TSMC's best-in-class silicon technology process and packaging technologies to advance accelerated infrastructure for the AI era."
About Marvell
To deliver the data infrastructure technology that connects the world, we're building solutions on the most powerful foundation: our partnerships with our customers. Trusted by the world's leading technology companies for over 25 years, we move, store, process and secure the world's data with semiconductor solutions designed for our customers' current needs and future ambitions. Through a process of deep collaboration and transparency, we're ultimately changing the way tomorrow's enterprise, cloud, automotive, and carrier architectures transform—for the better.
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This press release contains forward-looking statements within the meaning of the federal securities laws that involve risks and uncertainties. Forward-looking statements include, without limitation, any statement that may predict, forecast, indicate or imply future events, results or achievements. Actual events, results or achievements may differ materially from those contemplated in this press release. Forward-looking statements are only predictions and are subject to risks, uncertainties and assumptions that are difficult to predict, including those described in the "Risk Factors" section of our Annual Reports on Form 10-K, Quarterly Reports on Form 10-Q and other documents filed by us from time to time with the SEC. Forward-looking statements speak only as of the date they are made. Readers are cautioned not to put undue reliance on forward-looking statements, and no person assumes any obligation to update or revise any such forward-looking statements, whether as a result of new information, future events or otherwise.
2. Semiconductor Digest and Gartner, December 2024.
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SOURCE Marvell
FAQ
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