Welcome to our dedicated page for Synopsys news (Ticker: SNPS), a resource for investors and traders seeking the latest updates and insights on Synopsys stock.
Synopsys Inc. reports developments across electronic design automation, semiconductor intellectual property, silicon design, simulation and analysis solutions, and design services. Company news commonly covers AI-powered design flows, hardware-assisted verification, interface IP, multiphysics simulation, digital twin capabilities, and engineering software that supports chip, system, and product development.
Recurring updates also include customer and ecosystem work with semiconductor foundries, processor and GPU platforms, cloud infrastructure, aerospace programs, and other engineering users. Financial news centers on earnings releases, business outlook commentary, share repurchase activity, and the integration of Synopsys and Ansys technologies within the company’s expanded silicon-to-systems portfolio.
Synopsys (Nasdaq: SNPS) announces its collaboration with Microsoft on the Rapid Assured Microelectronics Prototypes (RAMP) program. This partnership aims to develop integrated circuit hardware prototypes that ensure security in design and manufacturing within Microsoft Azure. The RAMP initiative seeks to enhance semiconductor innovation for government applications, allowing for trusted design and verification solutions. Additionally, Synopsys is also collaborating with the U.S. Government to enhance security in integrated circuit devices through the Automatic Implementation of Secure Silicon (AISS) program.
Synopsys (Nasdaq: SNPS) will announce its first quarter fiscal year 2021 results on Feb. 17, 2021, after market close. A conference call featuring Aart de Geus and Trac Pham will commence at 2:00 p.m. PT (5:00 p.m. ET) to discuss the results. Financial information will be available on their corporate website prior to the call, and a live webcast will also be offered. A replay of the conference call will be accessible from 4:00 p.m. PT on the same day until the announcement of the second quarter results in May 2021.
Synopsys, Inc. (Nasdaq: SNPS) has demonstrated silicon proof of its DesignWare 112G Ethernet PHY IP in a 5nm FinFET process. This technology enhances performance, power efficiency, and area optimization for system-on-chip (SoC) designs. The DesignWare 112G PHY boasts zero bit-error rate in channels over 40dB, with power efficiency below five picojoules per bit. Synopsys combines this innovation with comprehensive support, including routing feasibility studies and signal integrity models, providing a robust solution for high-performance cloud computing applications.
Synopsys has launched the DesignWare Integrity and Data Encryption (IDE) Security Modules to enhance data protection for SoCs using PCI Express 5.0 and CXL 2.0 architectures. These modules feature AES-GCM algorithms for efficient encryption, decryption, and authentication, ensuring data confidentiality for high-performance systems. They are pre-verified with DesignWare Controller IP, facilitating rapid integration with reduced risk. The modules comply with both PCIe 5.0 and CXL 2.0 standards, supporting the secure design of advanced cloud and HPC systems.
On January 19, 2021, Synopsys (Nasdaq: SNPS) announced that Sondrel has adopted its Fusion Design and Verification Continuum platforms to enhance design and verification processes for complex system-on-chip (SoC) designs across various applications, including automotive and AI. This collaboration aims to improve design efficiency and quality, enabling Sondrel to produce power-efficient architectures. Their decision was influenced by Synopsys' proven record of power-efficient designs and overall performance metrics.
Synopsys (Nasdaq: SNPS) and Socionext have announced a collaboration to enhance the use of Synopsys' DesignWare HBM2E IP, aimed at improving memory throughput for AI and high-performance computing applications. The HBM2E IP operates at 3.6 Gbps and supports advanced SoC requirements, delivering an aggregated bandwidth of 460 GB/s. This integration allows Socionext to develop high-performance chips with competitive power efficiency, currently using 5-nm FinFET technology. The availability of Synopsys' HBM2/2E IP spans from 16-nm to 5-nm processes.
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Synopsys, a leader in electronic design automation, announced that CFO Trac Pham will present at the 23rd Annual Needham Growth Conference on January 11, 2021, at 1:15 p.m. ET. The event will feature a live audio webcast available on the Synopsys investor relations website, where a replay will also be accessible post-event. This conference provides an opportunity for investors to gain insights into Synopsys, the 15th largest software company globally, and its innovations in semiconductor IP and software security.
Synopsys has published a report revealing that the cost of poor software quality in the US reached $2.08 trillion in 2020, including software failures and technical debt. Key findings indicate that operational failures account for $1.56 trillion, an increase of 22% since 2018. Unsuccessful development projects contributed $260 billion, rising by 46%, while legacy software issues amounted to $520 billion. The report underscores the need for enhanced software quality amid rising cyber threats and offers recommendations for improvement.
Synopsys (Nasdaq: SNPS) announced that Amazon Web Services (AWS) has implemented its VCS Fine-Grained Parallelism technology on Arm-based Graviton2 servers. This deployment enhances the development and verification of advanced connectivity technology and system-on-chips (SoCs). The integration allows AWS to handle increased simulation workloads efficiently, providing higher throughput and lower costs for their datacenter chips. Synopsys aims to meet the rising demand for compute power as SoC designs become more complex, enabling faster time-to-market for customers.