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Cadence Design Systems develops electronic design automation software, design IP, and system design and analysis products for semiconductor and system engineering. Company updates commonly cover AI-driven chip design, certified design flows for advanced process nodes, digital twins, physics-based simulation, and computational software used from silicon design to electromechanical systems.
Recurring developments include collaborations with semiconductor, cloud and accelerated-computing partners; customer adoption of technologies such as Tensilica Vision DSP IP and Cadence ChipStack AI Super Agent; and financial results across EDA, IP, and system design and analysis. Cadence also reports on expanded simulation capabilities, including structural and multibody dynamics technologies added through the completed Hexagon design and engineering acquisition.
Cadence Design Systems announced the deployment of its Clarity 3D Solver by Butterfly Network, which enhances the design of its handheld ultrasound system. The 3D Solver improves model characterization speed five-fold while maintaining accuracy compared to alternatives. This innovation optimizes designs and ensures signal integrity, delivering high-quality ultrasound images rapidly. The partnership underscores Cadence's role in advancing healthcare technology.
Cadence Design Systems (CDNS) announced that Global Unichip Corporation (GUC) utilized its Innovus Implementation System to significantly enhance ASIC design efficiency. GUC achieved a 10% reduction in wirelength and 5% improvement in switching power, while reducing floorplan design time from weeks to days. This advancement supports GUC in meeting the rising demands for mobile, automotive, AI, and hyperscale computing applications, particularly as ASIC designs grow in complexity. Cadence remains committed to delivering advanced digital design solutions.
Cadence Design Systems has collaborated with TSMC and Microsoft to enhance productivity and scalability for semiconductor design through the Cadence CloudBurst Platform on Microsoft Azure. Their Tempus Timing Signoff Solution demonstrates distributed scalability, signoff efficiency for designs over 10 billion transistors, and significant reductions in compute costs. This partnership aims to expedite the design process, allowing clients to launch innovative products quicker while efficiently managing large-scale projects.
Cadence Design Systems will participate in a virtual fireside chat at the Wells Fargo TMT Summit on December 1, 2021, featuring Anirudh Devgan and John Wall. The event starts at 11:20 a.m. EST and will be streamed live on Cadence's investor relations page. Additionally, the presentation will be available for replay until 5:00 p.m. PST on December 17, 2021. This participation underscores Cadence's leadership in electronic design, stemming from over 30 years of expertise and innovative solutions across various markets.
Cadence Design Systems (Nasdaq: CDNS) will participate in a virtual fireside chat at the 45th Nasdaq Investor Conference on November 30, 2021, at 12:30 p.m. EST. Anirudh Devgan, president, and John Wall, CFO, will represent the company. The event will be accessible via webcast and archived for replay until December 17, 2021, at 5:00 p.m. PST. Cadence, a leader in electronic design with over 30 years of experience, focuses on Intelligent System Design and serves various innovative sectors.
Cadence Design Systems announces the qualification of its Integrity 3D-IC platform by Samsung Foundry, enabling advanced 2D-to-3D partitioning for improved power, performance, and area (PPA) in chip design. This solution automates the creation of memory-on-logic configurations for hyperscale computing, mobile, automotive, and AI applications. The platform enhances 3D stacking by reducing memory latency and wirelength, thus boosting CPU performance and facilitating comprehensive system analysis.
Cadence Design Systems (NASDAQ: CDNS) announced that Samsung Foundry has successfully utilized its Liberate Trio Characterization Suite to enhance the efficiency of 3nm production libraries. This advanced characterization suite expedited Samsung's time to market by improving productivity and reducing turnaround time compared to earlier nodes. Key features include a unified production-proven flow, machine learning capabilities, and cloud optimization, enabling scalable and reliable operations. The collaboration supports Cadence's Intelligent System Design strategy, enhancing design enablement across various applications.
Cadence Design Systems (CDNS) announced that Samsung Foundry has adopted the Cadence Tempus Timing Signoff Solution featuring a new SPICE-accurate aging analysis capability. This advancement aims to enhance the reliability of designs for automotive, aerospace, and consumer applications while improving power, performance, and area (PPA). The Tempus solution allows Samsung to validate designs with over 10 years of reliability, achieving up to 4.2% improved frequency and 10% better timing slack. This collaboration marks a significant step towards high-reliability device manufacturing.
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Cadence Design Systems (Nasdaq: CDNS) will participate in a virtual fireside chat at the Berenberg US CEO Conference on November 9, 2021. The discussion, featuring Anirudh Devgan and John Wall, will be available live at 1:00 p.m. EST and archived on the Cadence website for replay until December 17, 2021. Cadence, a leader in electronic design, focuses on Intelligent System Design™, providing innovative solutions across various industries. For more details, visit cadence.com/cadence/investor_relations.