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Cadence Design Systems develops electronic design automation software, design IP, and system design and analysis products for semiconductor and system engineering. Company updates commonly cover AI-driven chip design, certified design flows for advanced process nodes, digital twins, physics-based simulation, and computational software used from silicon design to electromechanical systems.
Recurring developments include collaborations with semiconductor, cloud and accelerated-computing partners; customer adoption of technologies such as Tensilica Vision DSP IP and Cadence ChipStack AI Super Agent; and financial results across EDA, IP, and system design and analysis. Cadence also reports on expanded simulation capabilities, including structural and multibody dynamics technologies added through the completed Hexagon design and engineering acquisition.
Cadence Design Systems (NASDAQ: CDNS) has launched a new DRAM verification solution aimed at enhancing the testing of complex system-on-chip (SoC) designs. This solution achieves up to 10X increased verification throughput, facilitating efficient IP-to-SoC-level verification for advanced designs with DDR interfaces. It complies with JEDEC standards while supporting various memory technologies, including LPDDR5x and DDR5. Cadence aims to bolster innovation in memory technologies, collaborating with industry leaders like Micron to accelerate ecosystem development.
Cadence Design Systems (NASDAQ: CDNS) announced that Microchip has deployed its Palladium Z2 Enterprise Emulation Platform, achieving 2X better emulation capacity and 1.5X faster run-time performance for ASIC product development. This upgrade enhances Microchip's efficiency in creating high-performance SoC solutions for data centers, reducing FPGA prototyping time and ensuring smoother software integration. With seamless interoperability between Palladium and Protium systems, Microchip can effectively manage verification workloads, meeting tight time-to-market demands.
Cadence Design Systems (Nasdaq: CDNS) announced a collaboration with Light to integrate the Cadence Tensilica Vision Q7 DSP into Light's Clarity Depth Perception Platform. This partnership focuses on enhancing depth perception for advanced driver-assistance systems (ADAS) using two or more cameras for improved accuracy. The DSP enables up to 10X faster processing compared to traditional quad-core CPUs, with ISO 26262 compliance for automotive safety. This integration is expected to significantly bolster real-time processing capabilities, aligning with Cadence's Intelligent System Design strategy.
Cadence Design Systems (CDNS) is set to release its fourth quarter and fiscal year 2021 financial results on February 22, 2022, at 2:00 PM Pacific Time. The event will be led by CEO Dr. Anirudh Devgan and CFO John Wall. An archive of the webcast will be accessible from 5:00 PM Pacific Time on the release date until 5:00 PM Pacific Time on March 18, 2022. Cadence is recognized for its expertise in electronic design and has been listed among the 100 Best Companies to Work For by Fortune Magazine for seven consecutive years.
Cadence Design Systems announced the deployment of its Clarity 3D Solver by Butterfly Network, which enhances the design of its handheld ultrasound system. The 3D Solver improves model characterization speed five-fold while maintaining accuracy compared to alternatives. This innovation optimizes designs and ensures signal integrity, delivering high-quality ultrasound images rapidly. The partnership underscores Cadence's role in advancing healthcare technology.
Cadence Design Systems (CDNS) announced that Global Unichip Corporation (GUC) utilized its Innovus Implementation System to significantly enhance ASIC design efficiency. GUC achieved a 10% reduction in wirelength and 5% improvement in switching power, while reducing floorplan design time from weeks to days. This advancement supports GUC in meeting the rising demands for mobile, automotive, AI, and hyperscale computing applications, particularly as ASIC designs grow in complexity. Cadence remains committed to delivering advanced digital design solutions.
Cadence Design Systems has collaborated with TSMC and Microsoft to enhance productivity and scalability for semiconductor design through the Cadence CloudBurst Platform on Microsoft Azure. Their Tempus Timing Signoff Solution demonstrates distributed scalability, signoff efficiency for designs over 10 billion transistors, and significant reductions in compute costs. This partnership aims to expedite the design process, allowing clients to launch innovative products quicker while efficiently managing large-scale projects.
Cadence Design Systems will participate in a virtual fireside chat at the Wells Fargo TMT Summit on December 1, 2021, featuring Anirudh Devgan and John Wall. The event starts at 11:20 a.m. EST and will be streamed live on Cadence's investor relations page. Additionally, the presentation will be available for replay until 5:00 p.m. PST on December 17, 2021. This participation underscores Cadence's leadership in electronic design, stemming from over 30 years of expertise and innovative solutions across various markets.
Cadence Design Systems (Nasdaq: CDNS) will participate in a virtual fireside chat at the 45th Nasdaq Investor Conference on November 30, 2021, at 12:30 p.m. EST. Anirudh Devgan, president, and John Wall, CFO, will represent the company. The event will be accessible via webcast and archived for replay until December 17, 2021, at 5:00 p.m. PST. Cadence, a leader in electronic design with over 30 years of experience, focuses on Intelligent System Design and serves various innovative sectors.
Cadence Design Systems announces the qualification of its Integrity 3D-IC platform by Samsung Foundry, enabling advanced 2D-to-3D partitioning for improved power, performance, and area (PPA) in chip design. This solution automates the creation of memory-on-logic configurations for hyperscale computing, mobile, automotive, and AI applications. The platform enhances 3D stacking by reducing memory latency and wirelength, thus boosting CPU performance and facilitating comprehensive system analysis.