Arteris Network-on-Chip IP Deployed in Renesas’ Next-Gen R-Car Automotive Technology

Rhea-AI Summary

Arteris (Nasdaq: AIP) announced its FlexNoC network-on-chip interconnect IP has been licensed and deployed in Renesas' R-Car Gen 5 automotive SoC series, including the sampling R-Car X5H.

Key technical highlights: 400 TOPS native AI acceleration, 4x+ chiplet boost potential, TSMC 3 nm process, and 30–35% power reduction versus prior generation while supporting ASIL D functional safety.

Positive

• 400 TOPS native AI acceleration in R-Car X5H
• Chiplet extensions can boost AI performance by 4x+
• 30–35% power reduction using TSMC 3 nm automotive process
• SoC designed to meet ISO 26262 ASIL D system-level safety

Negative

• R-Car X5H is currently sampling, indicating commercial volume is not yet established
• Design targets depend on TSMC 3 nm node availability and yields

Key Figures

AI acceleration: 400 TOPS AI performance scaling: 4x or more Process node: 3 nm +1 more

4 metrics

AI acceleration 400 TOPS R-Car X5H SoC AI acceleration performance

AI performance scaling 4x or more UCIe chiplet extensions boost AI performance

Process node 3 nm TSMC automotive process used for R-Car X5H SoC

Power reduction 30–35% Power consumption reduction vs prior generation processes

Market Reality Check

Price: $16.02 Vol: Volume 400,024 is below 2...

normal vol

$16.02 Last Close

Volume Volume 400,024 is below 20-day average 459,960 (relative volume 0.87x). normal

Technical Price 16.02 is trading above the 200-day MA at 12.75, reflecting a sustained uptrend into this news.

Peers on Argus

AIP gained 5.81% while peers were mixed: SKYT up 5.26%, POET up 1.0%, but LAES, ...

1 Up 1 Down

AIP gained 5.81% while peers were mixed: SKYT up 5.26%, POET up 1.0%, but LAES, NVEC, and CEVA in the main peer list were down. Momentum scanner shows CEVA up 10.67% and IMOS down 3.46%, indicating stock-specific moves rather than a unified sector trend.

Historical Context

5 past events · Latest: Feb 12 (Positive)

Pattern 5 events

Date	Event	Sentiment	Move	Catalyst
Feb 12	Deployment milestone	Positive	-2.0%	Announced NoC technology shipped in over 4 billion chips and chiplets.
Feb 12	Earnings & guidance	Positive	-2.0%	Reported Q4 and FY 2025 revenue growth and issued FY 2026 guidance.
Feb 11	Customer expansion	Positive	-1.2%	NXP expanded deployment of Arteris system IP across AI-enabled silicon.
Feb 02	Earnings date notice	Neutral	-4.3%	Announced timing of Q4 and full-year 2025 earnings release and call.
Jan 16	Inducement grants	Neutral	-4.7%	Disclosed 477,208 RSUs granted to 25 new employees as inducements.

Pattern Detected

Recent AIP news, including positive deployment and growth updates, often saw negative next-day reactions, indicating a pattern of selling into good news.

Recent Company History

Over the last few months, Arteris reported several notable milestones. On Feb 12, 2026, it highlighted deployment in over 4 billion chips and chiplets and strong variable royalty growth, alongside Q4 and full-year 2025 revenue growth of 30% and 22%, plus FY 2026 revenue guidance of $89.0–$93.0M. Earlier, NXP broadened deployment of Arteris system IP, and the company announced inducement RSU grants. Despite seemingly constructive news, 24h price reactions to these events were negative, contrasting with today’s positive move on the Renesas win.

Regulatory & Risk Context

Active S-3 Shelf

Shelf Active

Active S-3 Shelf Registration 2026-02-12

An effective S-3 shelf dated 2026-02-12 covers resale of up to 985,675 shares of common stock held by selling stockholders from the Cycuity acquisition. The company will not receive any proceeds from these secondary sales, so the registration facilitates liquidity for those holders without directly raising capital for Arteris.

Market Pulse Summary

This announcement highlights Arteris FlexNoC IP as the data-movement backbone for Renesas’ R-Car Gen...

Analysis

This announcement highlights Arteris FlexNoC IP as the data-movement backbone for Renesas’ R-Car Gen 5 X5H automotive SoC, delivering up to 400 TOPS and a 30–35% power reduction on TSMC’s 3 nm process while targeting ISO 26262 ASIL D. Recent history shows multiple design wins and robust revenue growth, but also recurring insider 10b5‑1 sales and an effective resale shelf for 985,675 Cycuity-related shares. Investors may watch future automotive design wins and royalty trends for confirmation of this trajectory.

Key Terms

network-on-chip (noc), adas, ucie, chiplet, +1 more

5 terms

network-on-chip (noc) technical

"its Arteris FlexNoC network-on-chip (NoC) interconnect IP has been licensed"

Network-on-chip is the built-in communication system that links multiple processors, memory blocks and peripherals inside a single semiconductor chip, using many tiny pathways and controllers to move data around. It matters to investors because it directly affects a chip’s speed, power consumption and ability to scale to more cores—impacting product performance, production cost and competitiveness much like a city’s road network affects traffic flow and growth.

adas technical

"Tailored for advanced driver-assistance (ADAS) and automated driving (AD) systems"

Advanced Driver Assistance Systems (ADAS) are electronic systems in vehicles that assist the driver with safety tasks. Examples include automatic emergency braking, lane keeping assist, and adaptive cruise control. These systems use sensors and cameras to improve vehicle safety.

ucie technical

"with UCIe protocol-based chiplet extensions to boost AI performance"

UCIe (Universal Chiplet Interconnect Express) is an industry standard for connecting small processor or memory building blocks, called chiplets, inside a single package so they work together like parts of a single chip. For investors, it matters because it can lower manufacturing costs, speed product development, and enable more flexible, high-performance semiconductors—similar to using interchangeable Lego pieces instead of carving one large block—potentially affecting makers’ competitiveness and profit margins.

chiplet technical

"The SoC and its chiplet extensions rely on Arteris NoC IP"

A chiplet is a small, specialized piece of a computer chip designed to be combined with other chiplets on a single package to create a larger, complete processor — think of it like Lego bricks that snap together to build different models. For investors, chiplets matter because they can lower manufacturing costs, improve production yields, and speed innovation by letting designers mix and match proven building blocks, affecting profit margins and competitive position in the semiconductor industry.

iso 26262 regulatory

"meet ISO 26262 automotive safety integrity level (ASIL D) requirements"

ISO 26262 is an international safety standard for the design and development of electrical and electronic systems in road vehicles, providing a rulebook and step‑by‑step checklist to prevent malfunctions that could lead to accidents. For investors, compliance signals lower regulatory, legal and commercial risk—reducing chances of costly recalls, delays or reputational damage—while lack of compliance can mean expensive redesigns, slower product launches and potential liability.

AI-generated analysis. Not financial advice.

FlexNoC interconnect IP with resilience option and advanced memory data traffic management enables Renesas to create power-efficient, low-latency, high-performance systems-on-chips (SoCs) with functional safety support for automated vehicles

CAMPBELL, Calif., March 24, 2026 (GLOBE NEWSWIRE) -- Arteris, Inc. (Nasdaq: AIP), a leading provider of semiconductor technology for accelerating innovation in the AI era, today announced that its Arteris FlexNoC network-on-chip (NoC) interconnect IP has been licensed and deployed by Renesas for its most advanced R-Car Gen 5 SoC series. Tailored for advanced driver-assistance (ADAS) and automated driving (AD) systems, the SoC and its chiplet extensions rely on Arteris NoC IP for the underlying data movement that is essential for high-performance, energy-efficient AI-enabled SoCs that will be used in future autonomous vehicles.

The latest R-Car X5H SoC, currently sampling, delivers high-speed image recognition and processes surrounding objects using automotive cameras, radar, and lidar. It delivers AI acceleration of up to 400 trillions of operations per second (TOPS) and with UCIe protocol-based chiplet extensions to boost AI performance by a factor of four or more. Its native NPU and GPU processing engines, along with Arm CPU clusters, are all connected via Arteris NoC interconnect IP technology for underlying data movement at top performance.

Developed leveraging the TSMC 3 nm automotive process, the X5H SoC achieves a 30% to 35% reduction in power consumption over the previous generation processes, lowering overall system costs by reducing the need for additional cooling solutions while also extending vehicle driving range. This is achieved while enabling customers to meet ISO 26262 automotive safety integrity level (ASIL D) requirements at the system level. Physical awareness, including support for advanced nodes in Arteris FlexNoC interconnect IP, and support for energy-efficient design make this possible.

“Arteris provides high-performance, physically aware, and flexible interconnect technology, which is increasingly needed to meet the advanced requirements of state-of-the-art, software-defined vehicles,” said Aish Dubey, VP and head of SoC division, high performance computing, Renesas Electronics Corporation. “Arteris FlexNoC IP enables us to achieve the performance, power reductions, and functional safety for our next-generation ADAS SoCs for level 2+, 3 and even level 4 automated vehicles, while supporting chiplet extensions to scale AI performance.”

“Intelligent automotive SoC compute platforms increasingly need to deliver a smarter, safer and more connected experience and scale with future AI mobility demands via chiplets extensions,” said K. Charles Janac, president and CEO of Arteris. “We are pleased to continue to expand our collaboration with Renesas, including the work on R-Car Gen 5 SoCs, and provide the underlying connectivity and enablement of high-performance, energy-efficient and safe data movement for automotive innovations.”

FlexNoC interconnect IP enables efficient, high-performance network-on-chip designs for complex SoCs. It improves SoC design success with its advanced physical awareness capability that minimizes development time, improves performance, lowers power consumption, and enables functional safety for mission-critical applications such as autonomous driving. Learn more about it and other solutions for automotive at arteris.com/automotive/.

About Arteris

Arteris is a leading provider of semiconductor technology that accelerates the creation of high-performance, power-efficient silicon with built-in safety, reliability, and security. Innovative Arteris products are designed to optimize data movement and help ease complexity in the modern AI era with network-on-chip (NoC) interconnect intellectual property (IP), system-on-chip (SoC) software for integration automation and hardware security assurance. All are used by the world’s top technology companies to improve overall performance and engineering productivity, reduce risk, lower costs, and bring cutting-edge designs to market faster. Learn more at arteris.com.

© 2004-2026 Arteris, Inc. All rights reserved worldwide. Arteris, Arteris IP, the Arteris IP logo, and the other Arteris marks found at https://www.arteris.com/trademarks are trademarks or registered trademarks of Arteris, Inc. or its subsidiaries. All other trademarks are the property of their respective owners.

Media Contact:
Arteris Inc.
Gina Jacobs
+1 408 560 3044
newsroom@arteris.com

This press release was published by a CLEAR® Verified individual.

FAQ

What did Arteris announce about its FlexNoC IP deployment in Renesas R-Car Gen 5 on March 24, 2026 (AIP)?

Arteris announced its FlexNoC NoC interconnect IP is licensed and deployed in Renesas R-Car Gen 5 SoCs. According to Arteris, the IP enables high-performance, energy-efficient data movement for AI-enabled automotive SoCs including the sampling R-Car X5H.

How much AI performance does the Renesas R-Car X5H deliver with Arteris FlexNoC (AIP) on March 24, 2026?

The R-Car X5H delivers up to 400 TOPS native AI acceleration. According to the company, UCIe chiplet extensions can boost AI performance by a factor of four or more for higher compute scaling.

What power improvements does Renesas claim for R-Car X5H built on TSMC 3 nm using Arteris IP (AIP)?

Renesas reports a 30%–35% power reduction versus the previous generation process. According to the company, lower power reduces cooling needs and can extend vehicle driving range.

Does the R-Car X5H support automotive functional safety standards relevant to investors (AIP)?

Yes, the R-Car X5H is designed to meet ISO 26262 ASIL D system-level requirements. According to Renesas, Arteris FlexNoC physical awareness and safety features help enable that functional safety support.

What is the commercial status of Renesas R-Car X5H and what does that mean for Arteris (AIP)?

The R-Car X5H is currently in sampling with customers, not yet in mass production. According to the companies, sampling implies technical validation is underway before potential volume shipments.